Abstract: A circuit and method for improving the metastable resolving time in low-power multi-state devices, including binary latches in integrated circuits. Upon detection of a metastable condition at the outputs of the integrated circuit, an increase in energy is locally applied to the decision making portion of the circuit. The localized application of energy to the decision making circuit reduces the metastability time constant tau (.tau.), thereby causing the circuit to resolve more rapidly to a stable operating state.

Abstract: An improved programmable logic device (PLD) comprises a programmable AND first array to which a set of PLD input lines are selectively connectable and providing a set of outputs which are selectively connectable to a set of inputs to a programmable OR second army which drives a second set of output lines, in combination with a programmable AND third array having a set of inputs that are selectively connectable to the set of input lines and having a set of outputs that are fixedly connected as a set of inputs to a fixed OR fourth array providing a set of PLD outputs, with the set of outputs from the OR second array also connected in a fixed manner as inputs to the OR fourth array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.

Abstract: A circuit formed with an input stage (20) and an output stage (22 or 28) uses capacitively enhanced switching to improve switching speed without significantly raising steady-state current utilization. The output stage contains a pair of amplifiers (A1and A2) that respond to complementary signals (V.sub.M1 and V.sub.M2) produced by the input stage. The amplifiers are coupled to a pair of corresponding nodes (N1 and N2). A third amplifier (A3) in the output stage has a control electrode coupled to one of the nodes, a flow electrode coupled to the other node, and another flow electrode coupled to a further node (N3). A current supply (24) provides current at the further node. A charge/discharge element (CD1) produces a capacitive-type charge/discharge action between the further node and a source of a reference voltage (V.sub.R1).

Abstract: A clocked S/R flip-flop having a master stage driving a slave stage. A logic signal at either a set or reset input of the maser stage charges one of a pair of capacitors respectively coupled to the outputs of a pair of FET devices respectively connected to such inputs and which are enabled during a clock pulse. The clock pulse also disables a pair of bipolar transistors respectively coupled to the outputs of the FET devices. The falling edge of the clock pulse enables the bipolar transistors, and the one which is connected to the charged capacitor produces a logic signal at the input of one of a pair of cross-coupled CMOS logic gates which constitute the slave stage. This produces a logic signal at the output of the slave stage corresponding to the binary value of the logic signal applied to the set or reset input of the master stage.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16). A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and an opposite-conductivity buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency. Connective regions (46) extend from the buried web to the upper semiconductor surface to contact electrical leads (54) typically arranged in a parallel pattern. The maximum dopant concentration in the intermediate cell regions occurs vertically within 20% of their mid-points.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.

Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.

Abstract: Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAs. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: A circuit technique for eliminating history-dependent skew and distortion of signals as they propagate through multiple gate stages in critical timing paths. It has been discovered that spurious effects can be attributed to signal coupling between stages, and that such coupling may be reduced by providing separate threshold voltage supplies for the critical gates. Each of the first and second gate stages comprises first and second transistors having their respective emitters coupled to a common circuit point, a current source coupled to the common circuit point to provide current flow through the transistors, with the relative current flow through said transistors being determined by the relative voltage levels at the respective bases. The output signal is taken from the collector of one of the transistors. First and second threshold voltage sources are coupled to the respective bases of the second transistors of the first and second gate stages.