Abstract: A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not.

Abstract: A system and method for maintaining cache coherency in a shared memory multiprocessor system. A plurality of multiprocessor elements are coupled to a network. The multiprocessor elements include a local cache memory, a local cache directory, a plurality of remote memory controllers, and a network interface chip which couples multiple processing elements to the network. A partial directory cache is stored in the local memory of the network interface unit. The partial directory cache is accessed to locate which one of the multiprocessing elements has a requested data element in the event of a local cache miss. Since the partial directory is stored in the local memory system of the network interface unit, this reduces the need to access the full directory stored in the slower, off-chip shared memory system. In the event of a miss in the partial directory cache, the full directory list stored in the off-chip shared memory system is accessed to find the location of the requested data element.

Abstract: A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not.

Abstract: Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.

Abstract: A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A separate line fill sequencer exists for each thread. Preferably, the I-cache is N-way set associative, where N is the number of threads, and includes an effective-to-real address table (ERAT), containing pairs of effective and real page numbers. ERAT entries are accessed by hashing the effective address. The ERAT entry is then compared with the effective address of the desired instruction to verify an ERAT hit. The corresponding real page number is compared with a real page number in the directory array to verify a cache hit. Preferably, the line fill sequencer operates in response to a cache miss, where there is an ERAT hit.

Abstract: An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of the segment registers. When a segment register is utilized to perform an effective-to-real address translation, which is stored in the effective-to-real address translation cache, the corresponding bit in the effective-to-real address translation cache segment register latch is set. In this way, a record is kept of which segment registers are currently mapped in the effective-to-real address translation cache. When a move to segment register instruction alters the content of a segment register, then the effective-to-real address translation cache segment register latch is examined to determine if that segment register has been mapped in the effective-to-real address translation cache. If so, then an effective-to-real address translation cache invalidation latch is set.

Abstract: A method, apparatus, and article of manufacture for performing thread switch tuning for optimal performance of a program executed by a computer data processing system having a multithreaded processor.