Abstract: A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block.

Abstract: Zero detect of a sum of binary operands is disclosed. If the sum is zero, the bit-complement of the sum is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the sum is non-zero, the bit-complement of the sum will contain one or more zero's, and therefore incrementing the bit-complemented sum will not generate a carry-out bit of one. One embodiment includes providing a result representing a bit-complement of the sum, and then inspecting a carry-out bit generated by incrementing the result. Another embodiment includes bit-complementing first and second operands, generating a first carry-out bit from a sum of the bit-complemented first and second operands and a constant of one, generating a second carry-out bit from a sum of the bit-complemented first and second operands and a constant of two, and setting a zero detect flag to TRUE when an EXCLUSIVE-OR of the first carry-out bit and the second carry-out bit is a one.

Abstract: The average of two signed or unsigned integer numbers (A, B) rounded away from zero as prescribed in the MPEG standard is calculated in one instruction cycle by right shifting each of the operands by one bit position, summing the shifted operands, and incrementing the result as appropriate. The shifted operands are summed in an adder (302) that provides two versions of the average, one being the sum of the shifted operands and the other being the sum-plus-one of the shifted operands. A multiplexer (310) under control of a control circuit (308) selects one of the sum and sum-plus-one outputs. Incrementing (selecting the sum-plus-one output) is based on inspection of the shifted-out bits of the operands, the most significant bit of the sum, and a mode signal indicative of whether the operands are signed or unsigned values.

Abstract: A method and apparatus for left-shifting a signed or unsigned integer operand and providing a clamped integer result in a single instruction cycle is disclosed. The apparatus includes a left-shifter for left-shifting the operand to obtain a shifted intermediate result and shifted-out bits. The apparatus also includes an overflow detector for generating an overflow signal in response to a sign bit of the operand, a sign bit of the shifted intermediate result, the shifted-out bits, and a mode signal indicative of whether the operand is signed or unsigned. The overflow signal has a first logical value when overflow occurs, and a second logical value in the absence of overflow.

Abstract: The n-bit average of four signed or unsigned n-bit integer operands (A, B, C and D) rounded away from zero as prescribed in the MPEG standard is calculated in one instruction cycle by appending two bits to a left side of each of the operands to provide four n+2 bit extended operands, summing the extended operands to provide an n+2 bit sum, removing the two least significant bits of the n+2 bit sum to provide an n-bit sum, and incrementing the n-bit sum as appropriate. An append circuit (302) appends two bits to the left sides of the operands, and the extended operands are coupled to an adder circuit (306) that includes adder logic (308) and an n-bit carry lookahead adder (310). The adder logic (308) provides the two least significant bits of the sum of the extended operands, along with n partial sum bits and n partial carry bits to the adder (310).