Abstract: A method for unlocking a locked operating system of an electronic device is provided. The electronic device includes a storage unit and a locking unit, the storage unit is configured for storing a preset password and preset unlocking request information. The method includes steps: receiving a message from a second electronic device; verifying the received message according to the preset unlocking request information; and sending the preset password to the second electronic device if the verification is successful.

Abstract: The invention provides processes of preparing a peptide including a GCC agonist sequence selected from the group consisting of SEQ ID NOs: 1-249 described herein.

Abstract: An aeration apparatus is provided. The aeration apparatus includes a raft, a cruising device, and an aeration device. The aeration device is installed on the raft. In use, the raft floats on a water surface, the cruising device propels the raft back and forth on the water surface, and the aeration device diffuses bubbles under the water surface.

Abstract: A method for offering services according to facial expressions is provided. The method has an electronic device storing a service database recording at least one user's information. The method activates an offering service function; captures facial expressions of the user; extracting the features of the facial expressions; compares the extracted features with the features in images of the facial expressions stored in the service database, so as to identify a corresponding feature stored in the service database, and determines the type of expression and the service corresponding thereto from images of the user stored in the service database; and activates and provides the determined service. An electronic device using the method is also provided.

Abstract: A method for unlocking a locked operating system of an electronic device is provided. The electronic device includes a storage unit and a locking unit, the storage unit is configured for storing a preset password and preset unlocking request information. The method includes steps: receiving a message from a second electronic device; verifying the received message according to the preset unlocking request information; and sending the preset password to the second electronic device if the verification is successful.

Abstract: An exemplary electronic device used for a synchronous control system includes an input unit, a communication unit, a storage unit, and a control module. The input unit includes at least one key including a unique key code. The storage unit stores a code table recording key codes of each of the at least one key. The control module executes the function associated with a key or a key combination manipulated by a user, and determines the key code associated with the key or the key combination. The control module further transmits the determined key codes to other electronic devices to control the other electronic devices to also execute the same instruction as the corresponding instruction associated with the determined key code associated with the key or the combination. A related method is also provided.

Abstract: Antisense oligonucleotides that inhibit expression of human replication-initiation protein as well as methods of preventing or treating hyperproliferative conditions using said oligonucleotides are disclosed. One aspect provides an antisense oligonucleotide that inhibits the expression of human replication-initiation protein and has a sequence complementary to at least a portion of a target sequence encoding a human replication-initiation gene. By administering a therapeutically effective amount of an antisense oligonucleotide or by contacting the hyperproliferating cells with an effective amount of one or more antisense oligonucleotides, expression of replication-initiation protein is inhibited. Methods of screening and testing active antisense oligonucleotides for their ability to inhibit gene expression are also disclosed.

Abstract: The invention provides low-dose formulations of guanylate cyclase-C (“GCC”) agonist peptides and methods for their use. The formulations of the invention can be administered either alone or in combination with one or more additional therapeutic agents, preferably an inhibitor of cGMP-dependent phosphodiesterase or a laxative.

Abstract: A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node.

Abstract: A high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. The node boards and the switch fabric boards routinely perform link integrity checks when operating in a normal mode such that each can independently initiate failover to working ports when a link failure is detected. Link failure is detected either by sending a link heartbeat message after the link has had no traffic for a predetermined interval, or after receiving a predetermined consecutive number of invalid packets. Once the link failure is resolved, operation resumes in normal mode.

Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Abstract: A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: The methods and the apparatuses of an aeration equipment are described. A floatable aeration equipment with mobility at least has a floatable apparatus, a plurality of aeration apparatuses, and a controller. The thrust causing the motion of the aeration equipment is generated from the aeration apparatuses while aerating. The moving directions and positions of aeration equipment are controlled by a controller, which switches on/off a power source of one or more selected aeration apparatus.

Abstract: Genetically engineered Streptomyces clavuligerus strains with improved capabilities to produce clavulanic acid are provided. The strains are genetically engineered by disrupting newly identified glyceraldehyde-3-phosphate dehydrogenase (GAPDH) genes. This results in an increased intracelluar pool of the clavulanic acid precursor D-glyceraldehyde-3-phosphate (D-G3P), and increased clavulanic acid production. Clavulanic acid production may be further increased by supplying arginine to the medium in which the S. clavuligerus is grown.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Abstract: Antisense oligonucleotides that inhibit expression of human replication- initiation protein as well as methods of preventing or treating hyperproliferative conditions using said oligonucleotides are disclosed. One aspect provides an antisense oligonucleotide that inhibits the expression of human replication-initiation protein and has a sequence complementary to at least a portion of a target sequence encoding a human replication-initiation gene. By administering a therapeutically effective amount of an antisense oligonucleotide or by contacting the hyperproliferating cells with an effective amount of one or more antisense oligonucleotides, expression of replication-initiation protein is inhibited. Methods of screening and testing active antisense oligonucleotides for their ability to inhibit gene expression are also disclosed.

Abstract: A fire and smoke control system for a long passage is utilized in a long passage with an inlet and an outlet. The fire and smoke control system for a long passage includes a first water spray curtain apparatus, a second water spray curtain apparatus, and at least one third water spray curtain apparatus. The first water spray curtain apparatus is fixed over the inlet, and the second water spray curtain apparatus is fixed over the outlet. The third water spray curtain apparatus is fixed on the top of the long passage between the inlet and the outlet to divide the long passage into several sections.