Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

Abstract: A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.

Abstract: A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder decodes the data stream to generate an inner decoded stream, comprising an erasure marker for performing an erasure marking process on the inner decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the inner decoded stream. An outer decoder then decodes the inner decoded stream with reference to the erasure indicator to generate the receiver output.

Abstract: A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.

Abstract: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.

Abstract: A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream using a polynomial error-check equation previously determined. Finally, an accumulator is used to accumulate a number of trials with respect to the error check operation and generates a nominal error-check number based on the number of the correct trials.

Abstract: An apparatus for generating a detected punctured position in punctured convolutional codes. A delay line circuit has a plurality of delay elements connected in series, storing a finite sequence of an input bit stream. A logic gate circuit, coupled to outputs of a part of the delay elements of the delay line circuit in accordance with a parity check polynomial, performs a logic operation to output a number stream. The number stream is accumulated for possible punctured positions and the one of the possible punctured positions with a minimal accumulated number is selected and determined as the detected punctured position.

Abstract: A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.

Abstract: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.

Abstract: A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.

Abstract: A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a plurality of determining criteria according to the first indication signal to determine reliability information corresponding to the inner-code decoded signal and to generate a second indication signal accordingly, and decoding the inner-code decoded signal with reference to the second indication signal to generate the output signal.

Abstract: An apparatus and method for determining a puncture position for a de-puncturing process. A stream of received symbols that corresponds to a code is received. A slicing unit slices the stream of received symbols to determine representative bits of the code to form a first bit stream. A delay line delays the first bit stream to generate a second bit stream. A convolutional decoder de-punctures and decodes the received symbol to generate a third bit stream. A puncture decision unit, coupled to the delay line and the convolutional decoder, selects the puncture position with one of possible puncture positions, and delivers the puncture position signal indicating the puncture position, and compares the second bit stream and the third bit stream to generate an error metric corresponding to the puncture position, and determines one of the possible puncture positions according to the error metric as a detected puncture position.

Abstract: A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream using a polynomial error-check equation previously determined. Finally, an accumulator is used to accumulate a number of trials with respect to the error check operation and generates a nominal error-check number based on the number of the correct trials.