Patents by Inventor Rong-Shen Lee
Rong-Shen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160043239Abstract: Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Hsiang-Hung Chang, Wen-Chih Chen, Chia-Wei Jui, Zhi-Cheng Hsiao, Cheng-Ta Ko, Rong-Shen Lee, Sheng-Shu Yang
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Patent number: 9111774Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.Type: GrantFiled: February 22, 2013Date of Patent: August 18, 2015Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Publication number: 20150097259Abstract: Conductive plug structures suitable for stacked semiconductor device package is provided, wherein large contact region between the conductive plug structures and the corresponding pads of devices can be achieved, to reduce electrical impedance. Therefore, package structures such as photosensitive device packages using the conductive plug structures have superior electrical performance and reliability.Type: ApplicationFiled: December 15, 2014Publication date: April 9, 2015Applicant: Industrial Technology Research InstituteInventors: Hsiang-Hung CHANG, Wen-Chih CHEN, Chia-Wei JUI, Zhi-Cheng HSIAO, Cheng-Ta KO, Rong-Shen LEE, Sheng-Shu YANG
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Patent number: 8810031Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: GrantFiled: December 30, 2010Date of Patent: August 19, 2014Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Publication number: 20120321108Abstract: An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area.Type: ApplicationFiled: August 23, 2012Publication date: December 20, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Min Lin, Chang-Ho Liou, Yu-Wei Huang, Ming-Daw Chen, Rong-Shen Lee
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Patent number: 8280081Abstract: An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area.Type: GrantFiled: December 25, 2008Date of Patent: October 2, 2012Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chang-Ho Liou, Yu-Wei Huang, Ming-Daw Chen, Rong-Shen Lee
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Patent number: 8243966Abstract: An assembly structure of flat speaker including at least two speaker units and one connecting structure is provided. Each speaker unit includes a first electrode, a vibrating film, and a second electrode. The connecting structure includes two conductive layers, and a first insulating layer. A first conductive layer is connected the first electrode through a contact area, and each has a first length and a third length parallel to the contact area. A second conductive layer is connected the second electrode through a contact area, and each has a second length and a fourth, a fifth length parallel to the contact area. The third length is less than or equal to a sum of the first lengths of the speaker units. A sum of the third, the fourth, and the fifth length is less than or equal to a sum of the first and second lengths.Type: GrantFiled: August 4, 2009Date of Patent: August 14, 2012Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chang-Ho Liou, Yu-Wei Huang, Ming-Daw Chen, Rong-Shen Lee
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Publication number: 20120178212Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.Type: ApplicationFiled: March 20, 2012Publication date: July 12, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8164165Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.Type: GrantFiled: June 20, 2006Date of Patent: April 24, 2012Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Publication number: 20110156249Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: ApplicationFiled: December 30, 2010Publication date: June 30, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 7948072Abstract: A wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.Type: GrantFiled: July 25, 2008Date of Patent: May 24, 2011Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Shu-Ming Chang, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee, Chi-Shih Chang
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Publication number: 20100158284Abstract: An assembly structure of flat speaker including at least two speaker units and one connecting structure is provided. Each speaker unit includes a first electrode, a vibrating film, and a second electrode. The connecting structure includes two conductive layers, and a first insulating layer. A first conductive layer is connected the first electrode through a contact area, and each has a first length and a third length parallel to the contact area. A second conductive layer is connected the second electrode through a contact area, and each has a second length and a fourth, a fifth length parallel to the contact area. The third length is less than or equal to a sum of the first lengths of the speaker units. A sum of the third, the fourth, and the fifth length is less than or equal to a sum of the first and second lengths.Type: ApplicationFiled: August 4, 2009Publication date: June 24, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Min Lin, Chang-Ho Liou, Yu-Wei Huang, Ming-Daw Chen, Rong-Shen Lee
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Publication number: 20100034402Abstract: An electrode connection structure of a speaker unit is provided. The speaker unit includes at least one electrode layer, which is made of a conductive material, or made of a non-conductive material with a conductive layer formed on a surface thereof. The electrode connection structure includes a conductive electrode and an adhesive material. The conductive electrode is used for providing power supply signals for the speaker unit to generate sounds. The adhesive material adheres the conductive electrode in parallel with a surface of the electrode layer. The adhesive material has adhesive characteristics, so as to electrically connect the conductive electrode and the electrode layer, in which the adhesive material is adhered to a side of the surface of the electrode layer closely adjacent to the conductive electrode with a certain area.Type: ApplicationFiled: December 25, 2008Publication date: February 11, 2010Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Chang-Ho Liou, Yu-Wei Huang, Ming-Daw Chen, Rong-Shen Lee
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Publication number: 20100020502Abstract: a wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Applicant: Industrial Technology Research InstituteInventors: Ra-Min Tain, Shu-Ming Chang, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee, Chi-Shih Chang
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Publication number: 20070090490Abstract: A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses.Type: ApplicationFiled: June 20, 2006Publication date: April 26, 2007Applicant: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 6590282Abstract: A stacked semiconductor package formed on a substrate arranged in a serpentine configuration and a method for such fabrication are disclosed. The package is formed by at least one substrate section formed on the substrate bonded to at least one IC die by a flip-chip bonding method. The substrate is then folded onto itself such that the backside of a first IC die is adhesively bonded to the backside of a second IC die. A heat sink may optionally be utilized in-between the IC dies during the adhesive bonding process to further enhance thermal dissipation. The substrate section may be bonded to a printed circuit board by a plurality of solder balls formed on an active surface of the substrate section. The present invention can be bonded to a printed circuit board either in a horizontal position or in a vertical position for saving more real-estate on the board.Type: GrantFiled: April 12, 2002Date of Patent: July 8, 2003Assignee: Industrial Technology Research InstituteInventors: Hsing-Seng Wang, Rong-Shen Lee, Chia-Chung Wang
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Patent number: 6536653Abstract: A one-step bumping/bonding process for forming a semiconductor package is disclosed. In the method, a first electronic substrate which has either a plurality of conductive pads or a plurality of recessed openings formed on top of a plurality of apertures through the substrate is first provided and aligned with a second electronic substrate that has a plurality of conductive pads with each aperture aligned to a conductive pad on the second substrate. A plurality of solder balls is then planted on top of the plurality of conductive pads or the plurality of recessed openings on the surface of the first electronic substrate by a pick-and-place technique. Alternatively, a plurality of solder paste may be printed by a thick film stencil printing process similarly in place of the plurality of solder balls.Type: GrantFiled: January 16, 2001Date of Patent: March 25, 2003Assignee: Industrial Technology Research InstituteInventors: Hsing-Seng Wang, Rong-Shen Lee, Chiang-Han Day
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Patent number: 6479321Abstract: The present invention discloses a method that applies one time of reflow after stacking a plurality of semiconductor elements to complete the packaging. The upper surface of the chip carrier substrate (opposite side to the chip) in a semiconductor packaging element is implanted with solder balls or coated with solder paste. After stacking a plurality of the semiconductor packaging elements together, a reflow is applied to achieve electrical and physical connections among substrates. If the semiconductor packaging elements are ultra-thin elements, then one only needs to implant solder balls or coat solder paste on the substrate top surface of the top semiconductor packaging element and the substrate bottom surface of the bottom semiconductor packaging element. The reflow will make the soldering material permeate through each layer of substrate, completing the electrical connection between substrates.Type: GrantFiled: March 23, 2001Date of Patent: November 12, 2002Assignee: Industrial Technology Research InstituteInventors: Hsing-Seng Wang, Rong-Shen Lee
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Patent number: 6459150Abstract: A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.Type: GrantFiled: August 17, 2000Date of Patent: October 1, 2002Assignee: Industrial Technology Research InstituteInventors: Enboa Wu, Tsung-Yao Chu, Hsin-Chien Huang, Rong-Shen Lee
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Publication number: 20020137255Abstract: The present invention discloses a method that applies one time of reflow after stacking a plurality of semiconductor elements to complete the packaging. The upper surface of the chip carrier substrate (opposite side to the chip) in a semiconductor packaging element is implanted with solder balls or coated with solder paste. After stacking a plurality of the semiconductor packaging elements together, a reflow is applied to achieve electrical and physical connections among substrates. If the semiconductor packaging elements are ultra-thin elements, then one only needs to implant solder balls or coat solder paste on the substrate top surface of the top semiconductor packaging element and the substrate bottom surface of the bottom semiconductor packaging element. The reflow will make the soldering material permeate through each layer of substrate, completing the electrical connection between substrates.Type: ApplicationFiled: March 23, 2001Publication date: September 26, 2002Inventors: Hsing-Seng Wang, Rong-Shen Lee