Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract: An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract: A method and an apparatus for detecting a man-in-the-middle attack, where the method includes receiving, by a macro evolved Node B (MeNB), a first check request message sent by a secondary evolved Node B (SeNB), where the first check request message includes first identifier information and a first data packet count value, generating a second check request message according to the first identifier information, sending the second check request message to a user terminal, receiving a first check response message generated by the user terminal according to the second check request message, where the first check response message includes second identifier information and a second data packet count value, determining, by the MeNB, that the man-in-the-middle attack exists between the SeNB and the user terminal when the first data packet count value is different from the second data packet count value.

Abstract: The present disclosure relates to a key generation method, a master eNodeB, a secondary eNodeB, and UE. The key generation method includes: determining a key parameter corresponding to a data radio bearer DRB; sending the key parameter to UE corresponding to the DRB, so that the UE generates a user plane key according to the key parameter and a basic key generated by the UE; receiving a basic key generated by a master eNodeB and sent by the master eNodeB; and generating the user plane key according to the key parameter and the basic key generated by the master eNodeB.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

Abstract: A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D) material layer over a substrate; calculating a mean thickness of the first 2D material layer; comparing the mean thickness of the first 2D material layer with a reference parameter; determining that the mean thickness of the first 2D material layer is not substantially equal to the reference parameter; and after the determining, epitaxially forming a second 2D material layer over the first 2D material layer.

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A multifunctional softening valve and a water processing apparatus thereof. The multifunctional softening valve comprises a valve body, an ejector, a movable valve plate, a fixed valve plate, and a saline water control valve. The valve body is provided with a water inlet, a water outlet, a water drainage port, and a salt absorbing branch runner. The valve body is provided with a through-hole in communication with a filter element upper portion, a filter element lower portion and an ejector inlet. An ejector outlet is in communication with the filter element lower portion. The salt absorbing branch runner is provided with a saline water inlet. The saline water inlet is provided with a saline water control valve. The fixed valve plate is provided with a plurality of through-holes, and the through-holes are distributed according to a distribution mode of equally dividing the cross section of the fixed valve plate into six parts, and the movable valve plate is fitted to the fixed valve plate.

Abstract: A control valve with a planar seal structure having a valve body with a water inlet, water outlet, and water drainage port. A spool with a planar seal structure and having fixed valve plate and movable valve plate is disposed in the valve body. The movable valve plate is rotationally fitted to the fixed valve plate. The fixed valve plate has a plurality of through-holes. One through-hole with an arc and fan shape is in communication with the water outlet. The outer diameter of the through-hole with an arc and fan shape is greater than that of another through-hole of the fixed valve plate. The through-hole is in communication with the valve body's water inlet. The fixed valve plate has at least one arc communicating blind hole. The through-holes of the fixed valve plate are mutually fitted with the communicating blind hole.

Abstract: A color wheel is suitable for being disposed at a transmission path of an illumination beam emitted from a light source of a projection device. The color wheel includes a disc. The disc is suitable for rotating with respect to an axis. The disc has a non-light converting region and a light converting region. The disc has a first reference surface and a second reference surface opposite to the first reference surface. The disc has a plurality of first disturbing portions and a plurality of second disturbing portions. The first disturbing portions are located at the first reference surface and in the non-light converting region. The second disturbing portions are located at the second reference surface and in the non-light converting region. The first disturbing portions and the second disturbing portions are structurally continuous relative to the disc.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Abstract: Parsing XML (extensible markup language) data by performing the following operations: (i) dividing the piece of markup language into a plurality of pre-parsing segments; (ii) assigning the pre-parsing segment to a pre-parsing processor thread of a plurality of pre-parsing processor threads; (iii) determining any parsing division point(s) occurring in the pre-parsing segment so that data corresponding to a single tabular record is between each consecutive pair of parsing division points; (iv) dividing the piece of language into a plurality of parsing segments defined by the parsing division points so that each parsing segment corresponds to a single tabular record; (v) assigning the parsing segment to a parsing processor thread of a plurality of parsing processor threads; and (vi) parsing to generate a parsed tabular record corresponding to the parsing segment.