Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Abstract: The present invention belongs to the technical field of offshore wind power construction and particularly relates to a system and a method for sealing expanded polymer-based pile shoes for a jacket. The system comprises a jacket disposed on a seabed, several pile shoes arranged around a lower end of the jacket, and several steel pipe piles inserted into the seabed, wherein the steel pipe piles are inserted into the corresponding pile shoes. The system is characterized in that gaps between the pile shoes and the steel pipe piles are respectively filled with concrete and an expanded high polymer from top to bottom, an annular elastic diaphragm is further connected to the inner walls of the pile shoes, and the expanded polymer is wrapped by the elastic diaphragm, such that the expanded polymer is isolated from the steel pipe piles and the concrete.

Abstract: A device (100) includes a substrate (101-106) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (107-108) defining an active device region; a dummy LDMOS device (121) in the active device region which includes a grounded drain (D1) in a drift region (105), a source (S1, S2) in a body region (109) which extends to contact the buried semiconductor layer, a gate electrode (G1-G4) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion (104) adjacent the DTI structure; and one or more active LDMOS devices (122) positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device (121) which reduces an electric field across the sidewall insulator layer (107) in the DTI structure.

Abstract: The present invention belongs to the field of offshore wind power and, in particular, relates to system for transporting hydrogen produced from seawater and method based on an existing offshore wind power plant. The system comprises a wind generator, a seawater electrolytic cell device and a hydrogen transporting unit, wherein the wind generator is configured for converting wind energy into electric energy, the seawater electrolytic cell device is configured for electrolyzing seawater by making using of electric energy supplied by the wind generator and the hydrogen transporting unit is configured for transporting hydrogen produced by the seawater electrolytic cell device to a land. According to the present invention, by combining offshore wind power with seawater hydrogen production, resource advantages of the offshore wind power plant is utilized fully, so that the seawater hydrogen production cost is lowered.

Abstract: Disclosed is a pile-cylinder-truss composite offshore wind turbine foundation. The pile-cylinder-truss composite offshore wind turbine foundation includes a truss structure, a suction cylinder and a pile foundation. The suction cylinder is connected to a bottom portion of the truss structure, and an embedded sleeve for mounting the pile foundation is provided on the suction cylinder. The embedded sleeve is located inside, at an edge of or outside the suction cylinder. The present invention also provides a construction process of the pile-cylinder-truss composite offshore wind turbine foundation.

Abstract: A device (100) includes a substrate (101-106) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (107-108) defining an active device region; a dummy LDMOS device (121) in the active device region which includes a grounded drain (D1) in a drift region (105), a source (S1, S2) in a body region (109) which extends to contact the buried semiconductor layer, a gate electrode (G1-G4) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion (104) adjacent the DTI structure; and one or more active LDMOS devices (122) positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device (121) which reduces an electric field across the sidewall insulator layer (107) in the DTI structure.

Abstract: The present invention is a grouting method for single pile rock-socketed foundation for offshore wind power, comprising: driving a steel casing into an overburden layer to dig the overburden layer and a rock stratum so as to dig a pile hole; hoisting a steel pipe pile into the steel casing and positioning the steel pipe pile in the pile hole, wherein an annular cavity is formed between the inner walls of the steel pipe pile and the pile hole and the bottom of the steel casing; grouting a first grouting layer to the bottom of a pipe hole of the steel pipe pile; grouting a plurality of grouting layers into the upper end of the first grouting layer in the annular cavity; and pulling out the steel casing, wherein after a grouting solution is aged, the steel pipe pile is stably connected to the overburden layer and the rock stratum.

Abstract: A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Abstract: The present invention belongs to the technical field of offshore wind power construction and particularly relates to a system and a method for sealing expanded polymer-based pile shoes for a jacket. The system comprises a jacket disposed on a seabed, several pile shoes arranged around a lower end of the jacket, and several steel pipe piles inserted into the seabed, wherein the steel pipe piles are inserted into the corresponding pile shoes. The system is characterized in that gaps between the pile shoes and the steel pipe piles are respectively filled with concrete and an expanded high polymer from top to bottom, an annular elastic diaphragm is further connected to the inner walls of the pile shoes, and the expanded polymer is wrapped by the elastic diaphragm, such that the expanded polymer is isolated from the steel pipe piles and the concrete.

Abstract: An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

Abstract: A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

Abstract: An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

Abstract: An apparatus comprises a Laterally Diffused Metal Oxide Semiconductor (LDMOS) comprising a drain connectable to a drift region and a source connectable to a body region. A diode comprises a cathode electrically coupled to the drift region, wherein during an operating condition, the anode is charged to a bias voltage less than a high voltage applied to the drain and greater than a low voltage applied to the source. The anode is laterally displaced from the drain by a first distance. A first deep trench isolation (DTI) is proximate to the source and disposed to laterally surround the LDMOS. A shield junction is proximate to the first DTI and on an opposite side of the source, and electrically connected to the anode.

Abstract: A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.

Abstract: A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.

Abstract: A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area.

Abstract: Provided is a cable protection device for subsea cable in offshore wind farm, the cable protection system including: a connecting flange, an intermediate pipe body, a tapered connecting pipe, and a connector. The subsea cable protection device in offshore wind farm has the advantages of simple structure, no segmentation mould making in manufacturing process. During installation and use, the length of the intermediate pipe can be increased or decreased according to actual requirements. Moreover, the cable protection device can be connected to the cable steel tube on the wind turbine foundation via the connecting flange.

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.