Patents by Inventor Rotem Banin

Rotem Banin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES FOR GENERATING AN OSCILLATION SIGNAL
    Publication number: 20210265999
    Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.
    Type: Application
    Filed: August 5, 2019
    Publication date: August 26, 2021
    Inventors: Ofir DEGANI, Igal KUSHNIR, Elan BANIN, Rotem BANIN
  • Transceiver with inseparable modulator demodulator circuits
    Patent number: 11095427
    Abstract: A transceiver, including a modulation circuit configured to modulate a first digital word into a first modulated time signal; and a demodulation circuit configured to demodulate a second modulated time signal into a second digital word, wherein the modulation and demodulation circuits are operable without an external clock source, and inseparably share one or more same circuit elements. Also, a tunable delay line may be configured to set a time rate of the modulation, wherein the modulation circuit and the demodulation circuit inseparably share the tunable delay line.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Rotem Banin, Elan Banin, Ofir Degani, Ronen Gernizky, Ashoke Ravi
  • FREQUENCY ESTIMATION
    Publication number: 20210116871
    Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
    Type: Application
    Filed: June 26, 2017
    Publication date: April 22, 2021
    Inventors: Sarit Zur, Igal Kushnir, Gil Horovitz, Rotem Banin, Sergey Bershansky
  • Phase interpolator, apparatus for phase interpolation, digital-to-time converter, and methods for phase interpolation
    Patent number: 10972085
    Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 6, 2021
    Assignee: Intel IP Corporation
    Inventors: Sebastian Sievert, Sarit Zur, Ofir Degani, Rotem Banin
  • Frequency doubler pulse limiter and methods for limiting pulse widths produced by a frequency doubler
    Patent number: 10958255
    Abstract: This disclosure provides devices and methods for limiting the duration of pulses resulting from frequency modulation so as to provide for better propagation of a frequency doubler output within a communication device. The frequency doubler may be configured to receive a frequency doubler input and produce a modified frequency doubler output, wherein the frequency doubler includes a first flip-flop gate configured to receive a data input, a reset input, and a clock input and produce a first gate output; a first delay control configured to receive the gate output and produce a first delayed control output; and a first logic gate configured to receive the delayed control output and the frequency doubler input and produce a first logic gate output, wherein the modified frequency doubler output is based on the first logic gate output.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Gil Asa, Assaf Ben-Bassat, Ofir Degani, Shahar Gross, Rotem Banin, Uri Grosglik
  • Apparatus, system and method of generating a frequency output with a digitally controlled ring oscillator (DCRO)
    Patent number: 10840923
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 17, 2020
    Assignee: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop
    Patent number: 10768580
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel IP Corporation
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • Circuit, apparatus, digital phase locked loop, receiver, transceiver, mobile device, method and computer program to reduce noise in a phase signal
    Patent number: 10707880
    Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 7, 2020
    Assignee: Intel IP Corporation
    Inventors: Elan Banin, Tamar Marom, Gil Horovitz, Rotem Banin
  • Time encoded data communication protocol, apparatus and method for generating and receiving a data signal
    Publication number: 20200212943
    Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.
    Type: Application
    Filed: September 17, 2018
    Publication date: July 2, 2020
    Inventors: Elan Banin, Eytan Mann, Rotem Banin, Ronen Gernizky, Ofir Degani, Igal Kushnir, Shahar Porat, Amir Rubin, Vladimir Volokitin, Elinor Kashani, Dmitry Felsenstein, Ayal Eshkoli, Tal Davidson, Eng Hun Ooi, Yossi Tsfati, Ran Shimon
  • DPLL with adjustable delay in integer operation mode
    Patent number: 10686451
    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Apple Inc.
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Nati Dinur, Gil Horovitz, Rotem Banin
  • Divider-less fractional PLL architecture
    Patent number: 10659061
    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20200091608
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 19, 2020
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • DPLL WITH ADJUSTABLE DELAY IN INTEGER OPERATION MODE
    Publication number: 20200067513
    Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 27, 2020
    Inventors: YAIR DGANI, Michael Kerner, Elan Banin, Nati Dinur, Gil Horovitz, Rotem Banin
  • Apparatus and a method for generating a radio frequency signal
    Patent number: 10516563
    Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 24, 2019
    Assignee: Intel IP Corporation
    Inventors: Sebastian Sievert, Ofir Degani, Ashoke Ravi, Rotem Banin
  • TIME-TO-DIGITAL CONVERTER, DIGITAL PHASE-LOCKED LOOP, METH-OD FOR OPERATING A TIME-TO-DIGITAL CONVERTER, AND METHOD FOR A DIGITAL PHASE-LOCKED LOOP
    Publication number: 20190384230
    Abstract: A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.
    Type: Application
    Filed: March 2, 2017
    Publication date: December 19, 2019
    Inventors: Yair Dgani, Michael Kerner, Elan Banin, Evgeny Shumaker, Gil Horovitz, Ofir Degani, Rotem Banin, Aryeh Farber, Rotem Avivi, Eshel Gordon, Tami Sela
  • Device and method to reduce power amplifier power consumption
    Patent number: 10477476
    Abstract: A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Michael Kerner, Uri Perlmutter, Avishay Friedman, Rotem Banin, Tzvi Maimon
  • DIVIDER-LESS FRACTIONAL PLL ARCHITECTURE
    Publication number: 20190334533
    Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.
    Type: Application
    Filed: December 27, 2016
    Publication date: October 31, 2019
    Inventors: Elias Nassar, Eyal Fayneh, Inbar Falkov, Elan Banin, Rotem Banin, Ofir Degani, Samer Nassar
  • APPARATUS, SYSTEM AND METHOD OF GENERATING A FREQUENCY OUTPUT WITH A DIGITALLY CONTROLLED RING OSCILLATOR (DCRO)
    Publication number: 20190253058
    Abstract: For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.
    Type: Application
    Filed: September 29, 2016
    Publication date: August 15, 2019
    Applicant: INTEL IP CORPORATION
    Inventors: Ashoke Ravi, Rotem Banin, Ofir Degani, David Ben-Haim, Yigal Kalmanovich
  • Scalable interleaved digital-to-time converter circuit for clock generation
    Patent number: 10218379
    Abstract: Some embodiments include apparatus and methods using a first digital-to-time converter (DTC) circuit to receive an input clock signal and generate a first clock signal based on the input clock signal, a second DTC circuit to receive the input clock signal and generate a second clock signal based on the input clock signal, and an output circuit to receive the first and second clock signals to generate an output clock signal based on the first and second clock signals.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Rotem Banin, Elias Nassar, Inbar Falkov, Eyal Fayneh, Ofir Degani, Sebastian Sievert
  • CIRCUIT, APPARATUS, DIGITAL PHASE LOCKED LOOP, RECEIVER, TRANSCEIVER, MOBILE DEVICE, METHOD AND COMPUTER PROGRAM TO REDUCE NOISE IN A PHASE SIGNAL
    Publication number: 20190052279
    Abstract: A circuit is configured to reduce a noise component of a measured phase signal. The circuit includes an input for a phase signal of an oscillator and an error signal estimator configured to determine parity information and an estimated error amplitude in the phase signal based on the parity information. The circuit further includes a combiner configured to provide the measured phase signal with the reduced noise component based on a combination of the phase signal and the estimated error amplitude.
    Type: Application
    Filed: January 24, 2017
    Publication date: February 14, 2019
    Inventors: Elan Banin, Tamar Marom, Gil Horovitz, Rotem Banin