Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

Abstract: Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.

Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.

Abstract: Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO.

Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.

Abstract: A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that estimates the un-quantized phase associated with a quantization output of the time-to-digital converter. The time-to-digital converter generates a quantized value as the quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock. The estimation component estimates a phase value from the quantized values as a function of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.

Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.

Abstract: Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO.

Abstract: Some demonstrative embodiments include devices, systems and/or methods of wireless communication over a plurality of wireless communication frequency channels. For example, a wireless communication device may include a frequency source to generate a source frequency signal; a plurality of local-oscillator (LO) generators to generate a respective plurality of different carrier signal frequencies based on the source frequency signal; and a plurality of radio-frequency (RF) paths to simultaneously communicate over the plurality of carrier signal frequencies, respectively.

Abstract: A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2N values, and the fine delay/phase segment comprises 2N interpolators. Each interpolator is coupled to the even and odd coarse phase signals and is controlled by the fine delay/phase control signal to be responsive to the even coarse phase signal or the odd coarse phase signal based on a value of the fine delay/phase control signal.

Abstract: Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO.

Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/?1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.

Abstract: A Digital-to-Time (DTC) for a Digital Polar Transmitter (DPT) comprises a coarse delay/phase segment and a fine delay/phase segment. The coarse delay/phase segment generates an even delay/phase signal and an odd delay/phase signal. The fine/phase delay segment receives the even coarse phase signal and the odd coarse phase signal, and is responsive to a fine delay/phase control signal to generate a fine delay/phase output signal that is an interpolation of the even delay/phase signal and the odd delay/phase signal. In one exemplary embodiment, the fine delay/phase control signal comprises a binary signal having 2N values, and the fine delay/phase segment comprises 2N interpolators. Each interpolator is coupled to the even and odd coarse phase signals and is controlled by the fine delay/phase control signal to be responsive to the even coarse phase signal or the odd coarse phase signal based on a value of the fine delay/phase control signal.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of out-put signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.