Patents by Inventor Roubik Gregorian

Roubik Gregorian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8917582
    Abstract: A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation unit, operating in a digital domain, that receives a first digital echo estimate signal from an LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 23, 2014
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Publication number: 20110044216
    Abstract: A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals. respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.
    Type: Application
    Filed: October 29, 2010
    Publication date: February 24, 2011
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Publication number: 20110044397
    Abstract: A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation unit, operating in a digital domain, that receives a first digital echo estimate signal from an LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.
    Type: Application
    Filed: October 29, 2010
    Publication date: February 24, 2011
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Patent number: 7843859
    Abstract: A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment, a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals, respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 30, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Patent number: 7839758
    Abstract: A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation filter unit, operating in a digital domain, that receives a first digital echo estimate signal from a LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo estimate signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: November 23, 2010
    Assignee: Net Logic Microsystems, Inc.
    Inventors: Roubik Gregorian, Gaurav Malhotra
  • Patent number: 7127021
    Abstract: A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: October 24, 2006
    Assignee: Exar Corporation
    Inventors: Shin Chung Chen, Roubik Gregorian, Mir Bahram Ghaderi, Vincent Sing Tso
  • Patent number: 6906593
    Abstract: A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element provides the ability to programmably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: June 14, 2005
    Assignee: Exar Corporation
    Inventors: Bahram Fotouhi, Roubik Gregorian
  • Publication number: 20050073364
    Abstract: A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element provides the ability to progammably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Applicant: Exar Corporation
    Inventors: Bahram Fotouhi, Roubik Gregorian
  • Patent number: 6798857
    Abstract: A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: September 28, 2004
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Shih-Chung Fan
  • Publication number: 20040012414
    Abstract: A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.
    Type: Application
    Filed: July 19, 2002
    Publication date: January 22, 2004
    Applicant: Exar Corporation
    Inventors: Shin Chung Chen, Roubik Gregorian, Mir Bahram Ghaderi, Vincent Sing Tso
  • Publication number: 20030190001
    Abstract: A converting circuit which converts RZ data into intermeidate NRZ data. The intermediate NRZ data is then sampled to detect a phase of the intermediate NRZ data, which corresponds to the phase of the RZ data. In a preferred embodiment, the converting circuit is incorporated in a modified Hogge NRZ phase detector. A toggle flip-flop is placed in front of the Hogge phase detector. Since the toggle flip-flop is triggered by the leading edge of the RZ pulse, it essentially converts the RZ data into intermediate NRZ data. An exclusive-OR gate samples two different output stages of the Hogge NRZ phase detector, with the output stages being separated by an interim stage to provide a clock delay. The output of the exclusive-OR gate is an intermediate NRZ signal that corresponds to the input RZ data stream, which can then be sampled. The exclusive-OR gates inside the Hogge phase detector are used, as in the Hogge phase detector, to produce the up and down signals provided to a charge pump that is part of a PLL.
    Type: Application
    Filed: April 8, 2002
    Publication date: October 9, 2003
    Applicant: Exar Corporation
    Inventors: Roubik Gregorian, Mir Bahram Ghaderi, James Ban Ho, Vincent Sing Tso
  • Patent number: 6452425
    Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: September 17, 2002
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Manop Thamsirianunt
  • Publication number: 20020109533
    Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 15, 2002
    Applicant: Exar Corporation
    Inventors: Roubik Gregorian, Manop Thamsirianunt
  • Publication number: 20020097808
    Abstract: A digital LBO in which digitized versions of the desired waveforms are stored in memory. A selection circuit allows the selection of certain ones of said waveforms corresponding to an anticipated amount of signal degradation over a transmission line. A digital-to-analog converter converts those certain waveforms into analog waveforms for transmission.
    Type: Application
    Filed: December 1, 2000
    Publication date: July 25, 2002
    Applicant: Exar Corporation
    Inventors: Roubik Gregorian, Shin-Chung Fan
  • Publication number: 20020067788
    Abstract: A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 6, 2002
    Applicant: Exar Corporation, including cover sheet
    Inventors: Roubik Gregorian, Shih-Chung Fan
  • Patent number: 6351165
    Abstract: A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is positive or negative. When the counter reaches a pre-specified up or down count, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: February 26, 2002
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Shih-Chung Fan
  • Patent number: 6333651
    Abstract: A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to an integration circuit. The phase detector also indicates whether the phase difference is positive or negative. The output of the integration circuit is provided to a comparator, which compares the value to a threshold. When the threshold is exceeded, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: December 25, 2001
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Shih-Chung Fan
  • Patent number: 6300820
    Abstract: A voltage regulated charge pump is disclosed which is capable of regulating its output voltage without radiating switching noise or consuming more power than is necessary to maintain the output at its targeted level. The voltage regulated charge pump circuit and its method of regulation, according to the present invention, can reliably drive transmission lines in networking system and communication applications.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: October 9, 2001
    Assignee: Exar Corporation
    Inventors: Bahram Fotouhi, Roubik Gregorian
  • Patent number: 6121837
    Abstract: An operational amplifier that exhibits a relatively constant gain over process and temperature variations. The operational amplifier according to the present invention is designed such that its gain does not depend on process sensitive parameters such as mobility of field effect transistors.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: September 19, 2000
    Assignee: Exar Corporation
    Inventors: Roubik Gregorian, Saied Rafati
  • Patent number: 6031389
    Abstract: A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic levels, after the output signal has made most of its transition. In a preferred embodiment, each switched transistor is controlled by a comparator that generates its output by comparing the level of the output signal to a predetermined reference voltage.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: February 29, 2000
    Assignee: Exar Corporation
    Inventors: Bahram Fotouhi, Roubik Gregorian