Abstract: A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

Abstract: A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.

Abstract: A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.

Abstract: An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.

Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

Abstract: A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results.

Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

Abstract: A system and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

Abstract: A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.