Abstract: In an example, a semiconductor device includes a region of semiconductor material with a buried doped region of a first conductivity type. A first well region of the first conductivity type is in the region of semiconductor material and is electrically coupled to the buried doped region. A second well region of a second conductivity type is in the region of semiconductor material and has a first peak dopant concentration. A third well region of the second conductivity type abuts edges of the second well region. The third well region is interposed between the first well region and the second well region and has a second peak dopant concentration that is different than the first peak dopant concentration. A doped anode region of the second conductivity type is in the first well region, a doped cathode region of the first conductivity type is in the second well region, and a doped contact region of the second conductivity type is in the second well region.

Abstract: Methods of fabricating ESD protection devices include forming a single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40 V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly-doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40 V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

Abstract: A single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: An ESD protection device for protecting an integrated circuit (IC) against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier (SCR) device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

Abstract: The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate, source, and body connected to a common power supply rail. A low-density doped drain region extends in a length direction beyond the gate sidewall spacers of the transistor to provide a lower leakage current than would otherwise be exhibited by the protection device.

Abstract: ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type and composed of first and second regions, the first base well region having a higher doped concentration and the second base well region situated between the first base well region and a collector region having a second conductivity type opposite the first conductivity type, an emitter region within the first base well region having the second conductivity type, first and second floating regions within the first base well region, the first floating region having the second conductivity type between the emitter region and the seocond floating region, the second floating region having the first conductivity type between the first floating region and the second base well region. The floating regions within the first base well region are abutting and electrically connected.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: An electrostatic discharge protection device includes a buried layer having a plurality of heavily doped regions of a first conductivity type and a laterally diffused region between adjacent heavily doped regions, a semiconductor region over the buried layer, and a first well of the first conductivity type extending from a surface of the semiconductor region to a heavily doped region. The device includes a first transistor in the semiconductor region having an emitter coupled to the first terminal, and a second transistor in the semiconductor region having an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor.

Abstract: An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

Abstract: An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

Abstract: Electrostatic discharge (ESD) protection devices and methods. The ESD protection devices include a semiconductor substrate, a buried semiconducting layer, and an overlying semiconducting layer. The ESD protection devices also include a first bipolar device that includes a first bipolar device region, a first device base region, and a first device emitter region. The ESD protection devices also include a second bipolar device that includes a second bipolar device region, a second device well, a second device base region, and a second device emitter region. The ESD protection devices further include a sinker well that electrically separates the first bipolar device from the second bipolar device. The ESD protection devices are configured to transition from an off state to an on state responsive to receipt of greater than a threshold ESD voltage by the first device base region. The methods include methods of forming the ESD protection device.

Abstract: An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

Abstract: An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

Abstract: An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer.

Abstract: An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

Abstract: Electrostatic discharge (ESD) protection devices and methods. The ESD protection devices include a semiconductor substrate, a buried semiconducting layer, and an overlying semiconducting layer. The ESD protection devices also include a first bipolar device that includes a first bipolar device region, a first device base region, and a first device emitter region. The ESD protection devices also include a second bipolar device that includes a second bipolar device region, a second device well, a second device base region, and a second device emitter region. The ESD protection devices further include a sinker well that electrically separates the first bipolar device from the second bipolar device. The ESD protection devices are configured to transition from an off state to an on state responsive to receipt of greater than a threshold ESD voltage by the first device base region. The methods include methods of forming the ESD protection device.