Abstract: An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99).

Abstract: An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR?Vt1DC|˜0.

Abstract: An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that ?Vt1TR?Vt1DC?˜0.

Abstract: An electrostatic discharge (ESD) clamp (41, 51, 61, 71, 81, 91), coupled across input-output (I/O) (22) and common (GND) (23) terminals of a protected semiconductor SC device or IC (24), comprises, an ESD transistor (ESDT) (25) with source-drain (26, 27) coupled between the GND (23) and I/O (22), a first resistor (30) coupled between gate (28) and source (26) and a second resistor (30) coupled between ESDT body (29) and source (26). Paralleling the resistors (30, 32) are control transistors (35, 35?) with gates (38, 38?) coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC (24) is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41?, 41?; 71, 71?, 71?), each stage (41, 41+, 41?; 71, 71?, 71?) comprising first (T1, T1?, T1?, etc.) and second transistors (T2, T2?, T2?? etc.) having a common collector (52, 52?, 52?) and first (26, 26?, 26?) and second (36, 36?, 36?) emitters providing terminals (32, 42; 32?, 42?; 32?, 42?) of each clamp stage (41, 41?, 41?; 71, 71?, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42?) of the last stage (41?, 71?) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29?, 29?; 39, 39?, 39?) (e.g.

Abstract: A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the design layout file and compiles a netlist. The checking mechanism then determines the critical operating parameters of the identified ESD devices and determines if the parasitic devices will negatively effect ESD protection performance. The checking mechanism then determines if the intentional devices meet design specifications; eliminates parasitic devices which will not negatively effect ESD protection from the netlist, and retains those parasitic devices which may lead to ESD protection malfunction. Design layout verification and faults are then reported.

Abstract: A checking mechanism for complete full-chip ESD protection circuit design and layout verification at layout level identifies all of both intentional and parasitic ESD devices contained in the design layout file and compiles a netlist. The checking mechanism then determines the critical operating parameters of the identified ESD devices and determines if the parasitic devices will negatively effect ESD protection performance. The checking mechanism then determines if the intentional devices meet design specifications; eliminates parasitic devices which will not negatively effect ESD protection from the netlist, and retains those parasitic devices which may lead to ESD protection malfunction. Design layout verification and faults are then reported.