Abstract: Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

Abstract: Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

Abstract: Systems, methods, and circuitries are provided for calibrating a heater used to heat an adjustable resistance network during a trimming procedure. In one example, a circuit is provided that includes an adjustable resistance network including first resistance segments; a heater element thermally coupled to the adjustable resistance network; a calibration resistor including second resistance segments thermally coupled to the first resistance segments; and interface circuitry coupled to the calibration resistor.

Abstract: A structural element (10). The inventive structural element (10) includes a frame (12) comprised of a plurality of studs (40) arranged in two rows, a first row (40A) disposed along a first side of the frame (12) and a second row (40B) disposed along a second side of the frame (12), and a foam core (18) disposed within the frame (12) between the first and second rows of studs (40). In an preferred embodiment, the studs (40) each include an exterior face (52), at least one interior face (54), at least one hollow interior cell (70), and at least one opening (74) through an interior face (54) adapted to provide access to a cell (70), and the foam (18) is adapted to fill the interior of the frame (12), penetrating within the hollow cells (70) of the studs (40) through the interior face openings (74).

Abstract: A system and circuit for generating a variable sized hash output using a single hash and mixing function are disclosed. In one embodiment, a system for generating a variable sized hash output data includes a hash function module for generating an N bit hash result data by processing an M bit input data. The system also includes a mixing function module including a plurality of logic gates which implement a set of reversible arithmetic functions for generating an N bit hash output data by processing the N bit hash result data using the set of reversible arithmetic functions, where a subset of the N bit hash output data is used as the variable sized hash output data, and a size of the subset of the N bit hash output data is less than N bits.

Abstract: The present invention provides systems, methods and a computer program product for the management of electronic work items by providing uniform methodology across an enterprise. Work items are electronically received by an organization and routed to available users depending upon the business rules of the organization and certain parameters of the work items. Service level commitments may be assigned, tracked and reported as capturing standard reporting across the enterprise specifically with respect to electronic work items.

Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.

Abstract: An overcurrent protection circuit using a shunt resistor and the voltage drop across a switch to program a user-defined current limiting level. This protects the switch and the input power supply, as well as the load. The shunt resistor is connected to the input or output of the switch, and a temperature dependent current source, so that a voltage drop is generated across the shunt resistor. An amplifier is used to sense the voltage across the shunt resistor and the voltage drop across the switch. When the voltage drop across the switch exceeds the voltage drop across the shunt resistor, the amplifier will regulate the switch so that a voltage drop across the switch is equal to the voltage drop across the shunt resistor. In this way, a constant current through the switch can be achieved. A constant ratio between the current limiting level to the shunt resistor value can be achieved with this method, so the current limiting level is programmable by selecting the resistor value.

Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.

Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.

Abstract: A translinear network (34) has first (Q1, Q2, Q3, Q4) and second (Q4, Q3, Q5, Q6) translinear loops. A Trafton-Hastings clamp circuit (36) is connected to generate a piecewise-polynomial-continuous current IY, the value of which becomes undefined when current IX=0 due to a removable singularity in the transfer equation at this point. A current mirror (38) comprising a plurality of transistors (M1, M2, M3) is coupled to the Trafton-Hastings clamp circuit (36), and operates to add additional currents in transistors Q3 and Q5 to IX, when the Trafton-Hastings clamp transistor (Q7) conducts, so as to perturb the removable singularity in the transfer equation into the left half-plane.

Abstract: One aspect of the invention is an integrated circuit (613)comprising a current source (611) coupled to voltage source (610) and an output load (635). The integrated circuit (613) further comprises a charge pump (600) coupled to the current source (611) at a first node (612) and to the output load (635) at a second node (620) and a recirculation circuit (650) coupled to the first node (612) and the second node (620). The recirculation circuit (650) is operable to limit to a known value the current that flows between the second node (620) and the output load (635).

Abstract: A semiconductor chip bearing an alignment mark, particularly useful for wire bonder alignment on chips having bonding surfaces over the active circuits. The marks are fabricated on diagonal corners of the chip, and each mark consists of a pair of touching squares which are rotated about 90 degrees from each other in the opposite chip corners. The unique positioning of the marks, as well as the rotation provides both gross chip position features useful in mounting the chip on a lead frame, as well as fine alignment set-up or teaching aids for wire bonding. The small, high visual contrast features of the alignment mark are fabricated simultaneously with the top active metallization of the IC chip, and are not covered by passivation coating or additional metal layers.

Abstract: An integrated circuit comprises a first node (11) and a first stage charge pump (510) coupled to the first node (11) and to load circuitry (520). The first stage charge pump comprises a first capacitor (C1) coupled to a first signal source (&phgr;1), a second capacitor (C2) coupled to a second signal source (&phgr;2), a drain (24) of a first n-channel field effect transistor (MN1) coupled to the first capacitor (C1), and a source (20) of the first n-channel field effect transistor (MN1) coupled to the first node (11). A source (36) of a first p-channel field effect transistor (MP1) couples to a second node (12) and a gate (34) of the first p-channel field effect transistor (MP1) couples to the second capacitor (C2). The gate (34) and drain (32) of the first p-channel transistor (MP1) couple to the gate (22) and drain (24) of the first n-channel transistor (MN1), respectively.

Abstract: A system (10) for propagating a digital signal through a slew-rate limited node (18) includes a signal generator (12) which generates slowly-slewing signal (14). A signal conditioner (16) couples to signal generator (12) at node (18) to receive slowly-slewing signal (14), and produces rapidly-slewing signal (20). Signal conditioner (16) converts signal (14) into signal (20) to reduce the propagation delay from signal generator (12) to load (24) by comparing signal (14) with a low voltage threshold, VL, and a high voltage threshold, VH. Signal conditioner (16) employs memory device (92) to determine whether signal (14) is rising or falling upon crossing either threshold VL or VH.

Abstract: A controller for a power converter wherein there is provided a comparator having an output terminal and first and second input terminals. A switch-mode power train is coupled to the output terminal and operable to receive an unregulated input voltage and provide a regulated output voltage. A feedback network coupled to the switch-mode power train provides a voltage to the first input of the comparator. A ramp circuit includes a first capacitor divider having a first capacitor connected from a first input node to a first midpoint node and a second capacitor connected from the first midpoint node to a first reference voltage node and a second capacitor divider including a third capacitor connected from a second input node to a second midpoint node and a fourth capacitor connected from the second midpoint node to the first reference node. A first switch couples the first or second midpoint node to the second input of said comparator.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A circuit and method for implementing a MOSFET gate driver. Two bipolar NPN transistors (Q1, Q2), constructed to achieve rail-to-rail swings when driving a capacitive load (23) by overlapping their respective emitter regions (13) over their contained contact regions (19) to prolong internal device saturation and resulting turn-off delays, alternately connect the gate drive terminal (31) to either a supply terminal (HVDC) or an output terminal (29). Predrive circuitry for these transistors comprises NMOS transistors (M9, M18, M12 and M13). The NPN transistors are supplemented by a CMOS inverter (PMOS transistor M6 and NMOS transistor M17). A PMOS transistor (M7) provides additional base drive for transistor Q1 when the gate drive node is approaching the supply node. A diode (D2) protects transistor Q1 against base-emitter avalanche and protects transistor M7 from excessive drain-to-source voltages.

Abstract: A voltage regulator (10) is provided. A first bipolar transistor (24) has an emitter connected to a first node (NODE 6) and a base connected to a second node (NODE 5). A second bipolar transistor (30) is scaled N:1 with respect to the first bipolar transistor (24), N greater than one. The second bipolar transistor (30) has an emitter, a base, and a lateral collector. The base is connected to the second node (NODE 5). A first resistor (20) is connected between the first node (NODE 6) and an output node (NODE 2). A second resistor (32) is connected between the first node (NODE 6) and the emitter of the second bipolar transistor (30), and a third resistor (22) is connected between the first node (NODE 6) and a ground node (GND). A current sensing amplifier (12, 14, 34, 38 and 40) has a first input node (NODE 7) connected to the lateral collector of the first bipolar transistor (24) and a second input node (NODE 8) connected to the lateral collector of the second bipolar transistor (30).

Abstract: A low-power differential switching amplifier (200, 210, 220, 230) is provided which utilizes a unique technique of generating interlaced ramps. The interlacing of the ramps causes the ramp discharge time to be effectively zero, which produces exceptionally accurate sawtooth waveforms with virtually no distortion. The timing of the differential switching amplifier circuitry can be synchronized with an external clock. A voltage null point is produced in the differential amplifier where zero voltage at the input of the amplifier produces essentially zero power dissipation within the load, even if the load is low-Q or substantially resistive. Also, by use of a phase balancing technique, residual errors resulting from component mismatches, which would otherwise have imposed power losses upon the load, are nulled out automatically during the operation of the amplifier.