Abstract: A switch mode power converter (10) is provided. Converter (10) includes a switching cell (12) that transforms an input voltage at input port (22) to an output voltage at output port (24). Switching cell (12) is controlled by a fixed-period, variable on-time control signal from summing comparator (14). The period of the control signal is set by a driving circuit (20). The on time is set by first and second feedback circuits (16) and (18). First feedback circuit (16) provides a fast transient response. Second feedback circuit (18) provides an stable dc steady-state operating point.

Abstract: A programmable mixed-mode circuit (180) has both digital (215,217) and analog (120,120',120") circuit portions. The digital portion (215,217) is provided by programmable digital logic. The analog portion (120,120',120") has a variety of analog circuits, including voltage references (218), high-speed comparators (208,209) and circuits (80) that are selectively configurable to provide operational amplifier or comparator functions. The analog circuits (122-125) are interconnected by programmable switch elements (128-131,160-167) so that the connection of the analog circuits to one another, to input or output pins (A0-A3,B0-B3,C0-C3) and to the digital circuitry (215,217) can be programmed.

Abstract: A technique for which integrated circuit duty-cycle control or pulse width current limiting adaptively responds to the load, allowing a brief inrush current event upon startup of the load, while restricting long-term power dissipation to a lower value. Upon sensing an overcurrent condition, a duty cycle control circuit causes the output to be placed into a high duty-cycle mode of operation to provide sufficient power to the load. A thermal sense circuit provides additional control because if the overcurrent condition continues and the junction temperature rises to the thermal sense trip point, the duty cycle control circuit places the output in a lower duty-cycle mode.

Abstract: A low power, break before make output circuit includes an output transistor pair 12 and 14, a first control circuit 20, a second control circuit 22, a first comparator 16, and a second comparator 18. First control circuit 20 has a first input coupled to a first digital control input and an output coupled to a control terminal of a first transistor 12 in the output transistor pair. Second control circuit 22 has a first input coupled to a second digital control input and an output coupled to a control terminal of a second transistor 14 in the output transistor pair. First comparator 16 has an input connected to the output of first control circuit 20 and an output connected to the second input of second control circuit 22. First comparator 16 compares a voltage at the control terminal of first transistor 12 to a first predetermined voltage and formulates a voltage at its output in response to the comparison.

Abstract: A method and apparatus are disclosed for sustaining efficiency of switched mode power converters over wide load ranges. The method and apparatus can be used with any switched mode power converter having at least one synchronous rectifier (Q.sub.2) capable of being enabled or disabled and coupled, either by direct connection or otherwise, to an inductor (L.sub.1) and a diode rectifier (D.sub.1), to provide a current path for the inductor current when the synchronous rectifier (Q.sub.2) is disabled. The power converter is initialized by enabling the synchronous rectifier (Q.sub.2). Occasionally, the synchronous rectifier (Q.sub.2) is disabled, and the energy stored in the inductor (L.sub.1) is detected by sensing a voltage representative of the energy stored in the inductor (L.sub.1). A power level signal is then generated indicating whether the power converter is operating above a selected threshold.