Patents by Inventor Roy Arthur Carruthers
Roy Arthur Carruthers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7102234Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: GrantFiled: April 19, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Patent number: 7098476Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: GrantFiled: September 24, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
-
Patent number: 7081676Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 22, 2003Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Patent number: 6815329Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: GrantFiled: April 2, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
-
Patent number: 6809030Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: June 28, 2002Date of Patent: October 26, 2004Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20040195695Abstract: A method of reducing the contact resistance of metal suicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: ApplicationFiled: April 19, 2004Publication date: October 7, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral,, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Patent number: 6753606Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.Type: GrantFiled: November 27, 2001Date of Patent: June 22, 2004Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Ronnen Andrew Roy, Yun Yu Wang
-
Publication number: 20040087160Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: ApplicationFiled: October 22, 2003Publication date: May 6, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20040077140Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
-
Publication number: 20030068883Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.Type: ApplicationFiled: November 5, 2002Publication date: April 10, 2003Applicant: International Business Machines CorporationInventors: Atul Champaklal Ajmera, Cyril Cabral, Roy Arthur Carruthers, Kevin Kok Chan, Guy Moshe Cohen, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Patent number: 6503641Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.Type: GrantFiled: December 18, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Chao-Kun Hu, Kim Yang Lee, Ismail Cevdet Noyan, Robert Rosenberg, Thomas McCarroll Shaw
-
Patent number: 6503833Abstract: A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.Type: GrantFiled: November 15, 2000Date of Patent: January 7, 2003Assignee: International Business Machines CorporationInventors: Atul Champaklal Ajmera, Cyril Cabral, Jr., Roy Arthur Carruthers, Kevin Kok Chan, Guy Moshe Cohen, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Publication number: 20020182836Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2layer in said structure.Type: ApplicationFiled: June 28, 2002Publication date: December 5, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul David Agnello, Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20020158337Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.Type: ApplicationFiled: April 2, 2002Publication date: October 31, 2002Inventors: Katherina E. Babich, Roy Arthur Carruthers, Timothy Joseph Dalton, Alfred Grill, Jeffrey Curtis Hedrick, Christopher Vincent Jahnes, Ebony Lynn Mays, Laurent Perraud, Sampath Purushothaman, Katherine Lynn Saenger
-
Publication number: 20020151158Abstract: Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.Type: ApplicationFiled: June 11, 2002Publication date: October 17, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Patent number: 6444578Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.Type: GrantFiled: February 21, 2001Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, Kevin K. Chan, Guy M. Cohen, Kathryn Wilder Guarini, James M. Harper, Christian Lavoie, Paul M. Solomon
-
Patent number: 6440851Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.Type: GrantFiled: October 12, 1999Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Paul David Agnello, Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Christian Lavoie, Kirk David Peterson, Robert Joseph Purtell, Ronnen Andrew Roy, Jean Louise Jordan-Sweet, Yun Yu Wang
-
Publication number: 20020115262Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.Type: ApplicationFiled: February 21, 2001Publication date: August 22, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Roy Arthur Carruthers, Kevin K. Chan, Guy M. Cohen, Kathryn Wilder Guarini, James M.E. Harper, Christian Lavoie, Paul M. Solomon
-
Patent number: 6413859Abstract: Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.Type: GrantFiled: March 6, 2000Date of Patent: July 2, 2002Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Roy Arthur Carruthers, James McKell Edwin Harper, Paul Michael Kozlowski, Christian Lavoie, Joseph Scott Newbury, Ronnen Andrew Roy
-
Publication number: 20020076574Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−XHfx, Ta1−XInxy, Ta1−XSnx, Ta1−XZrx.Type: ApplicationFiled: December 18, 2000Publication date: June 20, 2002Applicant: International Business Machines CorporationInventors: Cyril Cabral, Roy Arthur Carruthers, James McKell Edwin Harper, Chao-Kun Hu, Kim Yang Lee, Ismail Cevdet Noyan, Robert Rosenberg, Thomas McCarroll Shaw