Patents by Inventor Roy E. Greeff
Roy E. Greeff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180269875Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.Type: ApplicationFiled: March 30, 2018Publication date: September 20, 2018Applicant: Micron Technology, Inc.Inventor: Roy E. Greeff
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Patent number: 9948300Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.Type: GrantFiled: March 20, 2017Date of Patent: April 17, 2018Assignee: Micron Technology, Inc.Inventor: Roy E. Greeff
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Publication number: 20170212695Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Timothy Hollis, Roy E. Greeff
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Patent number: 9196321Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.Type: GrantFiled: October 3, 2013Date of Patent: November 24, 2015Assignee: Micron Technology, Inc.Inventors: Brian W. Huber, Vijay Vankayala, Brian Gross, Gary Howe, Roy E. Greeff
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Patent number: 9154131Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.Type: GrantFiled: March 12, 2013Date of Patent: October 6, 2015Assignee: Micron Technology, Inc.Inventors: Roy E. Greeff, David K. Ovard
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Publication number: 20150098285Abstract: Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory die responsive to a chip select signal, and to change the impedance of an on-die termination circuit of the memory die responsive to the detecting.Type: ApplicationFiled: October 3, 2013Publication date: April 9, 2015Applicant: Micron Technology, Inc.Inventors: Brian W. Huber, Vijay Vankayala, Brian Gross, Gary Howe, Roy E. Greeff
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Patent number: 8400810Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.Type: GrantFiled: June 17, 2011Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventors: Roy E. Greeff, David K. Ovard
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Publication number: 20110248743Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.Type: ApplicationFiled: June 17, 2011Publication date: October 13, 2011Inventors: Roy E. Greeff, David K. Ovard
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Patent number: 7965532Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.Type: GrantFiled: August 28, 2007Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Roy E. Greeff, David K. Ovard
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Patent number: 7746095Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: June 8, 2009Date of Patent: June 29, 2010Assignee: Round Rock Research, LLCInventors: George E. Pax, Roy E. Greeff
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Patent number: 7746959Abstract: A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.Type: GrantFiled: May 11, 2006Date of Patent: June 29, 2010Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Joo S. Choi, George E. Pax, Ronnie M. Harrison, David Ovard, Dragos Dimitriu, Troy A. Manning, Roy E. Greeff, Greg King, Brian Johnson
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Publication number: 20090243649Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Inventors: George E. Pax, Roy E. Greeff
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Patent number: 7577212Abstract: A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.Type: GrantFiled: August 30, 2004Date of Patent: August 18, 2009Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Joo S. Choi, George E. Pax, Ronnie M. Harrison, David Ovard, Dragos Dimitriu, Troy A. Manning, Roy E. Greeff, Greg King, Brian Johnson
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Patent number: 7557601Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: October 9, 2007Date of Patent: July 7, 2009Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff
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Publication number: 20090063789Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Inventors: Roy E. Greeff, David K. Ovard
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Patent number: 7444559Abstract: A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.Type: GrantFiled: January 28, 2004Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventors: Travis E. Swanson, Roy E. Greeff
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Patent number: 7282947Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: September 28, 2005Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff
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Patent number: 7245145Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: June 11, 2003Date of Patent: July 17, 2007Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff
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Patent number: 7242213Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: September 1, 2004Date of Patent: July 10, 2007Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff
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Patent number: 6937057Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: June 11, 2003Date of Patent: August 30, 2005Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff