Patents by Inventor Roy Edward Meade

Roy Edward Meade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12321022
    Abstract: A photonic chip includes a substrate, an electrical isolation region formed over the substrate, and a front end of line (FEOL) region formed over the electrical isolation region. The photonic chip also includes an optical coupling region. The electrical isolation region and the FEOL region and a portion of the substrate are removed within the optical coupling region. A top surface of a the substrate within the optical coupling region includes a plurality of grooves configured to receive and align a plurality of optical fibers. The grooves are formed at a vertical depth within the substrate to provide for alignment of optical cores of the plurality of optical fibers with the FEOL region when the plurality of optical fibers are positioned within the plurality of grooves within the optical coupling region.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: June 3, 2025
    Assignee: Ayar Labs, Inc.
    Inventors: Mark Wade, Chen Sun, John Fini, Roy Edward Meade, Vladimir Stojanovic, Alexandra Wright
  • Patent number: 12313891
    Abstract: A plurality of lid structures include at least one lid structure configured to overlie one or more heat sources within a multi-chip-module and at least one lid structure configured to overlie one or more temperature sensitive components within the multi-chip-module. The plurality of lid structures are configured and positioned such that each lid structure is separated from each adjacent lid structure by a corresponding thermal break. A heat spreader assembly is positioned in thermally conductive interface with the plurality of lid structures. The heat spreader assembly is configured to cover an aggregation of the plurality of lid structures. The heat spreader assembly includes a plurality of separately defined heat transfer members respectively configured and positioned to overlie the plurality of lid structures. The heat spreader assembly is configured to limit heat transfer between different heat transfer members within the heat spreader assembly.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: May 27, 2025
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Vladimir Stojanovic
  • Publication number: 20250012982
    Abstract: A beam steering structure includes an alignment structure shaped to receive and align an optical fiber such that an axis of a core of the optical fiber is oriented in a first direction. The beam steering structure includes an end portion having an angled optical surface oriented at a non-zero angle relative to the first direction. The end portion is shaped and positioned so that light propagating along the first direction from the optical fiber passes through the end portion to reach the angled optical surface. A reflecting system is positioned on the angled optical surface across the first direction. The reflecting system is configured to reflect incident light propagating along the first direction into a first reflected beam of a first polarization and a second reflected beam of a second polarization. The first and second reflected beams are directed into first and second optical communication channels, respectively.
    Type: Application
    Filed: September 17, 2024
    Publication date: January 9, 2025
    Inventors: John Fini, Roy Edward Meade, Derek Van Orden, Mark Wade
  • Publication number: 20240310589
    Abstract: An optical input/output chiplet is disposed on a first package substrate. The optical input/output chiplet includes one or more supply optical ports for receiving continuous wave light. The optical input/output chiplet includes one or more transmit optical ports through which modulated light is transmitted. The optical input/output chiplet includes one or more receive optical ports through which modulated light is received by the optical input/output chiplet. An optical power supply module is disposed on a second package substrate. The second package substrate is separate from the first package substrate. The optical power supply module includes one or more output optical ports through which continuous wave laser light is transmitted. A set of optical fibers optically connect the one or more output optical ports of the optical power supply module to the one or more supply optical ports of the optical input/output chiplet.
    Type: Application
    Filed: May 27, 2024
    Publication date: September 19, 2024
    Inventors: Alexandra Wright, Mark Wade, Chen Sun, Vladimir Stojanovic, Rajeev Ram, Milos Popovic, Roy Edward Meade, Derek Van Orden
  • Patent number: 12092880
    Abstract: A beam steering structure includes an alignment structure shaped to receive and align an optical fiber such that an axis of a core of the optical fiber is oriented in a first direction. The beam steering structure includes an end portion having an angled optical surface oriented at a non-zero angle relative to the first direction. The end portion is shaped and positioned so that light propagating along the first direction from the optical fiber passes through the end portion to reach the angled optical surface. A reflecting system is positioned on the angled optical surface across the first direction. The reflecting system is configured to reflect incident light propagating along the first direction into a first reflected beam of a first polarization and a second reflected beam of a second polarization. The first and second reflected beams are directed into first and second optical communication channels, respectively.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: September 17, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: John Fini, Roy Edward Meade, Derek Van Orden, Mark Wade
  • Patent number: 12057332
    Abstract: A photoresist material is deposited, patterned, and developed on a backside of a wafer to expose specific regions on the backside of chips for etching. These specific regions are etched to form etched regions through the backside of the chips to a specified depth within the chips. The specified depth may correspond to an etch stop material. Etching of the backside of the wafer can also be done along the chip kerf regions to reduce stress during singulation/dicing of individual chips from the wafer. Etching of the backside of the chips can be done with the chips still part of the intact wafer. Or, the wafer having the pattered and developed photoresist on its backside can be singulated/diced before etching through the backside of the individual chips. The etched region(s) formed through the backside of a chip can be used for attachment of optical component(s) to the chip.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 6, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Chen Sun, Roy Edward Meade, Mark Wade, Alexandra Wright, Vladimir Stojanovic
  • Patent number: 12019269
    Abstract: A multi-chip package assembly includes a substrate, a first semiconductor chip attached to the substrate, and a second semiconductor chip attached to the substrate, such that a portion of the second semiconductor chip overhangs an edge of the substrate. A first v-groove array for receiving a plurality of optical fibers is present within the portion of the second semiconductor chip that overhangs the edge of the substrate. An optical fiber assembly including the plurality of optical fibers is positioned and secured within the first v-groove array of the second semiconductor chip. The optical fiber assembly includes a second v-groove array configured to align the plurality of optical fibers to the first v-groove array of the second semiconductor chip. An end of each of the plurality of optical fibers is exposed for optical coupling within an optical fiber connector located at a distal end of the optical fiber assembly.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: June 25, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Chong Zhang, Haiwei Lu, Chen Li
  • Patent number: 12014962
    Abstract: A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: June 18, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Anatol Khilo, Forrest Sedgwick, Alexandra Wright
  • Publication number: 20240187110
    Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 6, 2024
    Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
  • Publication number: 20240176081
    Abstract: A vertical integrated photonics chiplet assembly includes a package substrate and an external device connected to a top surface of the package substrate. A photonics chip is disposed within the package substrate The photonics chip includes optical coupling devices positioned at a top surface of the photonics chip. A plurality of conductive via structures are disposed within the package substrate in electrical connection with electrical circuits within the photonics chip. The plurality of conductive via structures are electrically connected through the package substrate to the external device. An opening is formed through the top surface of the substrate to expose a portion of the top surface of the photonics chip at which the optical coupling devices are positioned. An optical fiber array is disposed and secured within the opening such that a plurality of optical fibers of the optical fiber array optically couple to the optical coupling devices.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chong Zhang, Roy Edward Meade
  • Patent number: 11994724
    Abstract: An optical input/output chiplet is disposed on a first package substrate. The optical input/output chiplet includes one or more supply optical ports for receiving continuous wave light. The optical input/output chiplet includes one or more transmit optical ports through which modulated light is transmitted. The optical input/output chiplet includes one or more receive optical ports through which modulated light is received by the optical input/output chiplet. An optical power supply module is disposed on a second package substrate. The second package substrate is separate from the first package substrate. The optical power supply module includes one or more output optical ports through which continuous wave laser light is transmitted. A set of optical fibers optically connect the one or more output optical ports of the optical power supply module to the one or more supply optical ports of the optical input/output chiplet.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: May 28, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Alexandra Wright, Mark Wade, Chen Sun, Vladimir Stojanovic, Rajeev Ram, Milos Popovic, Roy Edward Meade, Derek Van Orden
  • Publication number: 20240170387
    Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 23, 2024
    Inventor: Roy Edward Meade
  • Patent number: 11916602
    Abstract: A remote memory system includes a substrate of a multi-chip package, an integrated circuit chip connected to the substrate, and an electro-optical chip connected to the substrate. The integrated circuit chip includes a high-bandwidth memory interface. An electrical interface of the electro-optical chip is electrically connected to the high-bandwidth memory interface. A photonic interface of the electro-optical chip is configured to optically connect with an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals received through the electrical interface from the high-bandwidth interface into outgoing optical data signals. The optical macro transmits the outgoing optical data signals through the photonic interface to the optical link. The optical macro also converts incoming optical data signals received through the photonic interface into incoming electrical data signals.
    Type: Grant
    Filed: February 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard
  • Publication number: 20240061181
    Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Inventors: Shahab Ardalan, Michael Davenport, Roy Edward Meade
  • Patent number: 11899251
    Abstract: A vertical integrated photonics chiplet assembly includes a package substrate and an external device connected to a top surface of the package substrate. A photonics chip is disposed within the package substrate. The photonics chip includes optical coupling devices positioned at a top surface of the photonics chip. A plurality of conductive via structures are disposed within the package substrate in electrical connection with electrical circuits within the photonics chip. The plurality of conductive via structures are electrically connected through the package substrate to the external device. An opening is formed through the top surface of the substrate to expose a portion of the top surface of the photonics chip at which the optical coupling devices are positioned. An optical fiber array is disposed and secured within the opening such that a plurality of optical fibers of the optical fiber array optically couple to the optical coupling devices.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 13, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Chong Zhang, Roy Edward Meade
  • Publication number: 20240014904
    Abstract: An interposer device includes a substrate that includes a laser source chip interface region, a silicon photonics chip interface region, an optical amplifier module interface region. A fiber-to-interposer connection region is formed within the substrate. A first group of optical conveyance structures is formed within the substrate to optically connect a laser source chip to a silicon photonics chip when the laser source chip and the silicon photonics chip are interfaced to the substrate. A second group of optical conveyance structures is formed within the substrate to optically connect the silicon photonics chip to an optical amplifier module when the silicon photonics chip and the optical amplifier module are interfaced to the substrate. A third group of optical conveyance structures is formed within the substrate to optically connect the optical amplifier module to the fiber-to-interposer connection region when the optical amplifier module is interfaced to the substrate.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventors: Chen Sun, Roy Edward Meade, Mark Wade, Alexandra Wright, Vladimir Stojanovic, Rajeev Ram, Milos Popovic, Derek Van Orden, Michael Davenport
  • Patent number: 11867944
    Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: January 9, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Roy Edward Meade, Chen Sun, Shahab Ardalan, John Fini, Forrest Sedgwick
  • Patent number: 11822128
    Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 21, 2023
    Assignee: Ayar Labs, Inc.
    Inventors: Shahab Ardalan, Michael Davenport, Roy Edward Meade
  • Patent number: 11823990
    Abstract: A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: November 21, 2023
    Assignee: Ayar Labs, Inc.
    Inventor: Roy Edward Meade
  • Publication number: 20230370170
    Abstract: A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 16, 2023
    Inventors: Roy Edward Meade, Vladimir Stojanovic, Chen Sun, Mark Wade, Hugo Saleh, Charles Wuischpard