Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: A massively parallel nodal computer system periodically collects and broadcasts usage data for an internal communications network. A node sending data over the network makes a global routing determination using the network usage data. Preferably, network usage data comprises an N-bit usage value for each output buffer associated with a network link. An optimum routing is determined by summing the N-bit values associated with each link through which a data packet must pass, and comparing the sums associated with different possible routes.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Nodes vary a choice of routing policy for routing data in the network in a semi-random manner, so that similarly situated packets are not always routed along the same path. Semi-random variation of the routing policy tends to avoid certain local hot spots of network activity, which might otherwise arise using more consistent routing determinations. Preferably, the originating node chooses a routing policy for a packet, and all intermediate nodes in the path route the packet according to that policy. Policies may be rotated on a round-robin basis, selected by generating a random number, or otherwise varied.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. An automated routing strategy routes packets through one or more intermediate nodes of the network to reach a destination. Some packets are constrained to be routed through respective designated transporter nodes, the automated routing strategy determining a path from a respective source node to a respective transporter node, and from a respective transporter node to a respective destination node. Preferably, the source node chooses a routing policy from among multiple possible choices, and that policy is followed by all intermediate nodes. The use of transporter nodes allows greater flexibility in routing.

Abstract: The present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation, coupled to the emulator system by a high-speed cable, provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded number of cycles to the burst clock logic via the high-speed cable. The host workstation then generates a trigger signal within the high-speed cable, which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. An automated routing strategy routes packets through one or more intermediate nodes of the network to reach a final destination. The default routing strategy is altered responsive to detection of overutilization of a particular path of one or more links, and at least some traffic is re-routed by distributing the traffic among multiple paths (which may include the default path). An alternative path may require a greater number of link traversals to reach the destination node.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Each node implements a respective routing strategy for routing data through the network, the routing strategies not necessarily being the same in every node. The routing strategies implemented in the nodes are dynamically adjusted during application execution to shift network workload as required. Preferably, adjustment of routing policies in selective nodes is performed at synchronization points. The network may be dynamically monitored, and routing strategies adjusted according to detected network conditions.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: An interactive tool is disclosed for visualizing performance data in real-time to enable adaptive performance optimization for an application running on a massively parallel computer system. The interactive tool may be used to visualize network congestion (and other) performance counters for an application as it runs on the parallel system in real-time. Further, a developer may use the interactive tool to experiment with various tuning options and optimization approaches on-the-fly.

Abstract: A method, apparatus and program product are provided for increasing the usable memory capacity of a logic simulation hardware emulator. The present invention performs an additional logic synthesis operation during model build to transform an original logical array within a logic model into a transformed logical array, such that a row within the transformed logical array includes a plurality of merged logical array rows from the original logical array. The invention further modifies read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.

Abstract: A technique for reducing the number of actions performed as part of a molecular modeling simulation is disclosed. For example, embodiments of the invention may be used to reduce the number of comparisons performed in a simulation of binding affinity between a first molecule (e.g., a protein receptor site) and a second molecule (e.g., a ligand). Because such a simulation is typically performed a very large number of times for even one particular first and second molecule, and is further performed for different combinations of first and second molecules, the effect of reducing the number of comparisons is leveraged and can provide a significant impact on overall simulation performance.

Abstract: The present invention enhances the Direct Access Stimulus (DAS) interface presently employed within a logic simulation hardware emulator to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator. The present invention accomplishes this by introducing a set of special logic within the logic model to provide an alternate source for selected signals, identifies the special logic so that it is subsequently connected directly to the DAS card interface, and adds information to a symbol table so that this special logic can be identified as signal accessible through the DAS card interface. At runtime, when the user control program accesses facilities that have been connected to the DAS card interface, a set of special routines automatically reference the symbol table information to access the special logic that is connected to the DAS card interface.

Abstract: Individual components of a parallel system perform system maintenance operations during the times that the components are idle waiting for synchronization with other components. When all applicable components reach synchronization, further performance of system maintenance is suspended until the component is again idle at another synchronization point. Preferably, the component is a node having at least one processor and a nodal memory in a multi-node system. A system maintenance operation is preferably an interruptible and resumable diagnostic, such as a memory check. Although the amount of time allotted to system maintenance varies by component, over many synchronization points the total times in each node are sufficient for the maintenance operation.

Abstract: A massively parallel nodal computer system periodically collects and broadcasts usage data for an internal communications network. A node sending data over the network makes a global routing determination using the network usage data. Preferably, network usage data comprises an N-bit usage value for each output buffer associated with a network link. An optimum routing is determined by summing the N-bit values associated with each link through which a data packet must pass, and comparing the sums associated with different possible routes.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Each node implements a respective routing strategy for routing data through the network, the routing strategies not necessarily being the same in every node. The routing strategies implemented in the nodes are dynamically adjusted during application execution to shift network workload as required. Preferably, adjustment of routing policies in selective nodes is performed at synchronization points. The network may be dynamically monitored, and routing strategies adjusted according to detected network conditions.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Nodes vary a choice of routing policy for routing data in the network in a semi-random manner, so that similarly situated packets are not always routed along the same path. Semi-random variation of the routing policy tends to avoid certain local hot spots of network activity, which might otherwise arise using more consistent routing determinations. Preferably, the originating node chooses a routing policy for a packet, and all intermediate nodes in the path route the packet according to that policy. Policies may be rotated on a round-robin basis, selected by generating a random number, or otherwise varied.

Abstract: A massively parallel computer system contains an inter-nodal communications network of node-to-node links. An automated routing strategy routes packets through one or more intermediate nodes of the network to reach a destination. Some packets are constrained to be routed through respective designated transporter nodes, the automated routing strategy determining a path from a respective source node to a respective transporter node, and from a respective transporter node to a respective destination node. Preferably, the source node chooses a routing policy from among multiple possible choices, and that policy is followed by all intermediate nodes. The use of transporter nodes allows greater flexibility in routing.

Abstract: The present invention provides a method, apparatus and program-product for a self-healing, reconfigurable logic emulation system, wherein if a signal wire becomes faulty in an emulation cable during an emulation run, the runtime software can automatically reconfigure the emulator to reroute the data destined for the faulty signal wire across a spare wire. Such a feature enables a user to restart the emulation run without having to recompile the simulation model to account for the hardware fault.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.