Abstract: A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches.

Abstract: The present invention provides an apparatus and method for using clock bursting to minimize command latency in a logic simulation hardware emulator/accelerator. The logic simulator hardware emulator/accelerator includes an emulator system having logic gate functions representing a design under test. The logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles. A host workstation is coupled to the emulator system by a high-speed cable. The host workstation provides control for the emulator system. In normal operation, the host workstation encodes a predefined number of clock cycles for the emulator to run, then transmits the encoded predefined number of cycles to the burst clock logic via a plurality of signals within the high-speed cable.

Abstract: A method and apparatus are provided for correlating trace data from asynchronous machines, such as asynchronous emulation machines. A data capture signal is received from each of the plurality of asynchronous machines. The data capture signal from each of the plurality of asynchronous machines is sampled. Then the sampled data capture signal from each of the plurality of asynchronous machines and a cycle count are stored. A trace synchronization system is coupled to each of the plurality of asynchronous machines for receiving the data capture signal from each of the plurality of asynchronous machines. The trace synchronization system operates no slower than the data capture signal from each of the plurality of asynchronous machines, so that no data capture signals are missed.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: A method and apparatus are provided for correlating trace data from asynchronous machines, such as asynchronous emulation machines. A data capture signal is received from each of the plurality of asynchronous machines. The data capture signal from each of the plurality of asynchronous machines is sampled. Then the sampled data capture signal from each of the plurality of asynchronous machines and a cycle count are stored. A trace synchronization system is coupled to each of the plurality of asynchronous machines for receiving the data capture signal from each of the plurality of asynchronous machines. The trace synchronization system operates no slower than the data capture signal from each of the plurality of asynchronous machines, so that no data capture signals are missed. The trace synchronization system includes a trace synchronization array for storing the sampled data capture signal from each of the plurality of asynchronous machines and a cycle count.

Abstract: In accordance with the present invention, a system for providing high-speed sequential modeling in a simulator or emulator environment is provided. The system includes a sequential control system (microprocessor board) which is attached directly to an emulator. The sequential control system cycles or operates at a higher speed than the emulator. This allows the sequential control system to execute multiple commands during each hardware emulation cycle so that the concurrent operations model within the accelerator/emulator and the sequential operations model within the sequential control system achieve a high degree of parallel operation, greatly enhancing system speed and performance. Further, the system includes direct high-speed connections between the sequential control system and the host workstation so that the control system can be programmed to execute a sequential model and/or to exchange data directly with the host without actually passing any information through the hardware emulator/accelerator.