Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer having a lower redox potential than said material, the sacrificial metal layer being electrically connected to said noble metal layer.

Abstract: A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer (8) against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer (12) having a lower redox potential than said material, the sacrificial metal layer (12) being electrically connected to said noble metal layer (8).

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.

Abstract: A colloidal metal seed formulation useful for catalytically activating a surface of a non-conductive dielectric substrate in an electroless plating process is provided. The colloidal metal seed formulation includes stannous chloride, palladium chloride, HCl and a surfactant selected from a diphenyloxide disulfonic acid or alkali or alkaline earth metal salt thereof, C30H50O10, an alcohol alkoxylate and mixtures thereof. A method of electroless plating of a conductive metal onto a non-conductive dielectric substrate using the colloidal metal seed formulation is also provided.

Abstract: A method for forming a dielectric structure. A first layer is formed, wherein the first layer includes a first fully cured photoimageable dielectric (PID) material. A sticker lays is nonadhesively formed on the first layer, wherein the sticker layer includes a partially cured PID material. A second layer is nonadhesively formed on the sticker layer, wherein the second layer includes a second fully cured PID material, wherein the sticker layer is nonadhesively sandwiched between the first layer and the second layer such that the sticker layer is in non-adhesive contact with the first layer and in non-adhesive contact with the second layer, and wherein the sticker layer is capable of remaining in non-adhesive contact with the first layer and the second layer until the sticker layer is subsequently subjected to additional curing.

Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Abstract: A dielectric structure, and an associated method of fabrication, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The partially cured PID layer be formed either in isolation, or by successively forming upon one of the fully cured PID layers: the first partially cured PID sheet, the power plane, and the second partially cured PID sheet. The first partially cured PID sheet and the second partially cured PID sheet is the result of partially curing, by radiative exposure, a first uncured PID sheet and a second uncured PID sheet, respectively. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer.

Abstract: A circuitized semiconductor substrate comprising a layer of dielectric material having holes therethrough, a catalyst seed layer lining the walls of the holes along the surface of the dielectric material, and a nickel layer in the openings and a layer of copper above the nickel layer, along with a method for its fabrication. The invention also provides copper-nickel laminate PTH barrels and methods for their fabrication.

Abstract: A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.

Abstract: A method of removing a metal skin from a through-hole surface of a copper-Invar-copper (CIC) laminate without causing differential etchback of the laminate. The metal skin includes debris deposited on the through-hole surface as the through hole is being formed by laser or mechanical drilling of a substrate that includes the laminate as an inner plane. Removing the metal skin combines electrochemical polishing (ECP) with ultrasonics. ECP dissolves the metal skin in an acid solution, while ultrasonics agitates and circulates the acid solution to sweep the metal skin out of the through hole. ECP is activated when a pulse power supply is turned on and generates a periodic voltage pulse from a pulse power supply whose positive terminal is coupled to the laminate and whose negative terminal is coupled to a conductive cathode. After the metal skin is removed, the laminate is differentially etched such that the copper is etched at a faster rate than the Invar.

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.

Abstract: A technique for forming an organic chip carrier or circuit board, having two voltage planes and at least two signal planes is provided which includes bonding a first layer of photolithographic dielectric material to a first metal layer and exposing the first layer of dielectric material to a pattern of radiation to provide at least one opening through the first layer of the dielectric material. A second metal layer is bonded to the first layer of photoimageable material on the opposite side from the first metal layer. Holes are etched in the first and second metal layers which correspond to and are larger than each of the patterns on said openings in the first layer of dielectric material. The exposed pattern on the first layer of dielectric material is then developed, with the openings in the first and second metal layers being larger than the corresponding developed opening in the first dielectric material.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board, The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Abstract: A process for selective plating of a metal onto a substrate surface is provided. The process includes laminating a layer of conductive metal onto a dielectric substrate; and providing thru holes extending through said layer of conductive metal and said dielectric substrate.A thin layer of conductive metal is plated on the walls of the thru holes; and a photoresist layer is applied to the surface of the conductive metal and selectively exposed and developed to provide a mask corresponding to the negative of the desired circuit pattern.The exposed metal that is not covered by the photoresist is removed and then the remaining photoresist is removed to thereby provide the desired circuit pattern. A conductive metal is plated on the pattern up to the desired thickness.

Abstract: Nodule formation in a continuous electroless copper plating system is minimized by independently controlling the dissolved oxygen contents on the plating solution in the bath and in the associated external piping. The level of dissolved oxygen in the plating tank is maintained at a value such that satisfactory plating takes place. At the point where the plating solution leaves the tank, additional oxygen gas is introducted into the solution so that the level of dissolved oxygen in the plating solution in the external piping is high enough to prevent any plating from taking place in the external piping and so that in the external piping the copper is etched or dissolved back into solution. At the end of the external piping, the dissolved oxygen level is reduced so that the dissolved oxygen level of the plating solution in the tank is maintained at the level where plating will take place.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surfaces of the printed circuit board. These plated through holes contain a bill composition.