Patents by Inventor Roy Lambertson

Roy Lambertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11672189
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: June 6, 2023
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 11063214
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 13, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20210193917
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Publication number: 20200259079
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Patent number: 10680171
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 9, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20190173006
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: January 30, 2019
    Publication date: June 6, 2019
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Patent number: 10224480
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20180130946
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 9831425
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 28, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20150380642
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 9159913
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20150029780
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: August 19, 2014
    Publication date: January 29, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20140014893
    Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.
    Type: Application
    Filed: September 12, 2013
    Publication date: January 16, 2014
    Applicant: Unity Semiconductor Corporation
    Inventors: Roy Lambertson, Lawrence Schloss
  • Patent number: 8565039
    Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 22, 2013
    Assignee: Unity Semiconductor Corporation
    Inventors: Roy Lambertson, Lawrence Schloss
  • Patent number: 8493771
    Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 23, 2013
    Assignee: Unity Semiconductor Corporation
    Inventors: Lawrence Schloss, Julie Casperson Brewer, Wayne Kinney, Roy Lambertson, Rene Meyer
  • Patent number: 8395928
    Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: March 12, 2013
    Assignee: Unity Semiconductor Corporation
    Inventors: Julie Casperson Brewer, Christophe Chevallier, Wayne Kinney, Roy Lambertson, Darrell Rinerson, Lawrence Schloss
  • Publication number: 20120300535
    Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.
    Type: Application
    Filed: August 9, 2012
    Publication date: November 29, 2012
    Applicant: Unity Semiconductor Corporation
    Inventors: Lawrence Schloss, Rene Meyer, Wayne Kinney, Roy Lambertson, Julie Casperson Brewer
  • Publication number: 20120286232
    Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: Unity Semiconductor Corporation
    Inventors: Roy Lambertson, Lawrence Schloss
  • Patent number: 8274817
    Abstract: An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: September 25, 2012
    Assignee: Unity Semiconductor Corporation
    Inventors: Lawrence Schloss, Julie Casperson Brewer, Wayne Kinney, Roy Lambertson, Rene Meyer
  • Patent number: 8254196
    Abstract: A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: August 28, 2012
    Assignee: Unity Semiconductor Corporation
    Inventors: Roy Lambertson, Lawrence Schloss