Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Abstract: a 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: A method of forming a semiconductor device includes forming a first interlevel dielectric (ILD) layer over one or more transistor structures formed on a substrate, the one or more transistor structures including an active area, source/drain contact and a gate conductor formed over the substrate; forming a first metal (M1) level trench in an upper portion of the first ILD layer, followed by forming vias in a lower portion of the first ILD layer, down to the source/drain contact and down to the gate conductor; and filling both the trench and vias with a conductive material, thereby resulting in a dual damascene metal process at and below the M1 level of the semiconductor device.

Abstract: A vertical wafer-to-wafer interconnect structure is provided in which a first wafer and a second wafer are mated by way of metal studs that extend from a surface of the first wafer. The metal studs extend from the surface of the first wafer into a corresponding through via of the second wafer. A polyimide coating is present in the through via on mated surfaces of the first and second wafers and on another surface of the second wafer not mated to the first wafer, thus the metal studs provide a continuous metal path from the first wafer through the second wafer. Since only metal studs for the vertical connection are used, no alpha radiation is generated by the metal studs.

Abstract: The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.

Abstract: The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.

Abstract: A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.

Abstract: A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).

Abstract: A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).

Abstract: A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.

Abstract: A resist composition and a method for forming a patterned feature on a substrate. The composition comprises a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, and a photosensitive acid generator. The method includes providing a composition including a photosensitive acid generator and a molecular glass having at least one fused polycyclic moiety and at least one base soluble functional group protected with an acid labile protecting group, forming a film of the composition on the substrate, patternwise imaging the film, wherein at least one region of the film is exposed to radiation or a beam of particles, resulting in production of an acid catalyst in the exposed region, baking the film, developing the film, resulting in removal of base-soluble exposed regions, wherein a patterned feature from the film remains following the removal.

Abstract: A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.