Patents by Inventor Roy Yu
Roy Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959874Abstract: A nanostructure includes a base layer including a surface. The nanostructure further includes nano-patterned features including non-random topography located on the surface of the base layer. The nanostructure also includes an encapsulating layer including a conductive material arranged on the nano-patterned features.Type: GrantFiled: November 29, 2018Date of Patent: April 16, 2024Assignee: International Business Machines CorporationInventors: Cristina Camagong, Hariklia Deligianni, Emily R. Kinser, Roy Yu
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Publication number: 20200176262Abstract: A method for forming a nanostructure includes coating an exposed surface of a base layer with a patterning layer. The method further includes forming a pattern in the patterning layer including nano-patterned non-random openings, such that a bottom portion of the non-random openings provides direct access to the exposed surface of the base layer. The method also includes depositing a material in the non-random openings in the patterning layer, such that the material contacts the exposed surface to produce repeating individually articulated nano-scale features. The method includes removing remaining portions of the patterning layer. The method further includes forming an encapsulation layer on exposed surfaces of the repeating individually articulated nanoscale features and the exposed surface of the base layer.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Cristina Camagong, Hariklia Deligianni, Damon B. Farmer, Andrei Fustochenko, Ying He, Emily R. Kinser, Yu Luo, Roy Yu
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Publication number: 20200173953Abstract: A nanostructure includes a base layer including a surface. The nanostructure further includes nano-patterned features including non-random topography located on the surface of the base layer. The nanostructure also includes an encapsulating layer including a conductive material arranged on the nano-patterned features.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Cristina Camagong, Hariklia Deligianni, Emily R. Kinser, Roy Yu
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Patent number: 7564118Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: GrantFiled: May 2, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20080230891Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: ApplicationFiled: May 2, 2008Publication date: September 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Patent number: 7388277Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: GrantFiled: January 12, 2005Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20080105976Abstract: A vertical wafer-to-wafer interconnect structure is provided in which a first wafer and a second wafer are mated by way of metal studs that extend from a surface of the first wafer. The metal studs extend from the surface of the first wafer into a corresponding through via of the second wafer. A polyimide coating is present in the through via on mated surfaces of the first and second wafers and on another surface of the second wafer not mated to the first wafer, thus the metal studs provide a continuous metal path from the first wafer through the second wafer. Since only metal studs for the vertical connection are used, no alpha radiation is generated by the metal studs.Type: ApplicationFiled: January 9, 2008Publication date: May 8, 2008Applicant: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu
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Patent number: 7354798Abstract: A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vias (12, 22) in the wafers connected to studs (27, 37). The studs connect to openings (13, 23) having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body (102) provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening (103) in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings (113) and studs (127) to form vertical heat conduction pathways between the wafers.Type: GrantFiled: December 20, 2002Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Roy Yu
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Publication number: 20070259291Abstract: The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.Type: ApplicationFiled: May 8, 2006Publication date: November 8, 2007Inventors: James Bucchignano, Gerald Gibson, Mary Rothwell, Roy Yu
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Publication number: 20070252287Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: June 20, 2007Publication date: November 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20060278998Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: August 9, 2006Publication date: December 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20060264036Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: July 24, 2006Publication date: November 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Tomothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Patent number: 7071031Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.Type: GrantFiled: May 28, 2003Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu
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Publication number: 20060121690Abstract: A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vias (12, 22) in the wafers connected to studs (27, 37). The studs connect to openings (13, 23) having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body (102) provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening (103) in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings (113) and studs (127) to form vertical heat conduction pathways between the wafers.Type: ApplicationFiled: December 20, 2002Publication date: June 8, 2006Inventors: H Pogge, Roy Yu
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Patent number: 7049697Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.Type: GrantFiled: June 26, 2003Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Chandrika Prasad, Roy Yu
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Patent number: 6998327Abstract: A thin film transfer join process in which a multilevel thin film structure is formed on a carrier, the multilevel thin film structure is joined to a final substrate and then the carrier is removed. Once the carrier is removed, the dielectric material and metallic material that were once joined to the carrier are now exposed. The dielectric material is then etched back so that the exposed metallic material protrudes beyond the dielectric material. Also disclosed is a module made by the foregoing process.Type: GrantFiled: November 19, 2002Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Jeffrey B. Danielson, Balaram Ghosal, James Kuss, Matthew Wayne Oonk, Chandrika Prasad, Eric Daniel Perfecto, Roy Yu
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Publication number: 20050173800Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.Type: ApplicationFiled: June 26, 2003Publication date: August 11, 2005Inventors: H. Pogge, Chandrika Prasad, Roy Yu
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Publication number: 20050127514Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: ApplicationFiled: December 8, 2003Publication date: June 16, 2005Inventors: Shyng-Tsong Chen, Stefanie Chiras, Matthew Colburn, Timothy Dalton, Jeffrey Hedrick, Elbert Huang, Kaushik Kumar, Michael Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Nitta, Sampath Purushothaman, Robert Rosenberg, Christy Tyberg, Roy Yu
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Publication number: 20050121711Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.Type: ApplicationFiled: January 12, 2005Publication date: June 9, 2005Inventors: H. Pogge, Roy Yu, Chandrika Prasad, Chandrasekhar Narayan
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Publication number: 20050056943Abstract: A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads.Type: ApplicationFiled: June 8, 2004Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: H. Pogge, Chandrika Prasad, Roy Yu