Patents by Inventor Roy Yu
Roy Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6444560Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. A stud is provided on the front surface of the chip, and a layer with interconnection wiring is formed on a transparent plate. The wiring layer includes a conducting pad on a surface thereof opposite the plate. A second layer is formed on top of the wiring layer, with a via formed therein to expose the conducting pad. The stud and via are then aligned and connected; the front surface of the chip thus contacts the second layer and the stud makes electrical contact with the conducting pad. A chip support is then attached to the device. An interface between the wiring layer and the plate is exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density.Type: GrantFiled: September 26, 2000Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: H. Bernhard Pogge, Chandrika Prasad, Roy Yu
-
Patent number: 6339527Abstract: The capacitor on a ceramic substrate one by unique film metallization including in one embodiment an in situ oxidation of titanium to create a metal oxide capacitor. The combination of metals when used with the appropriate optimized oxidation conditions and parameters ensures a high yielding capacitor with high capacitance in absence of noble metals and with ease of manufacture providing a low cost, high yield capacitor on ceramic.Type: GrantFiled: December 22, 1999Date of Patent: January 15, 2002Assignee: International Business Machines CorporationInventors: Mukta S. Farooq, John U. Knickerbocker, Srinivasa S. N. Reddy, Robert A. Rita, Roy Yu
-
Patent number: 6331731Abstract: A component of a module includes a column therethrough that conducts heat or equalizes the density of a surface of the component to enhance the uniformity of the etch of the surface. The module includes an integrated circuit chip that is connected therein by a controlled collapse chip contact/connection method. The component is a cap or insulator layer.Type: GrantFiled: December 7, 1995Date of Patent: December 18, 2001Assignee: International Business Machines CorporationInventors: Kimberley Anne Kelly, Roy Yu
-
Patent number: 6323045Abstract: A method and structure for providing top-to-bottom repair of a defective I/O net in a thin film transfer and join process. At least one C4 location and at least one capture pad are provided on a thin film substrate. The substrate is preferably ceramic. The C4 location of the defective net is severed by removal of a delete strap. The corresponding solder connection of the associated capture pad is also removed. A spare C4 location and capture pad are connected to provide a Z-repair line imbedded in the TF wiring structure. The Z-repair line is wired to the defective net.Type: GrantFiled: December 8, 1999Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Christopher Cline, Nancy W. Hannon, Chandrika Prasad, Thomas A. Wassick, Roy Yu
-
Publication number: 20010037565Abstract: A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.Type: ApplicationFiled: June 21, 2001Publication date: November 8, 2001Inventors: Chandrika Prasad, Roy Yu, Richard L. Canull, Giulio DiGiacomo, Ajay P. Giri, Lewis S. Goldmann, Kimberley A. Kelly, Bouwe W. Leenstra, Voya R. Markovich, Eric D. Perfecto, Sampath Purushothaman, Joseph M. Sullivan
-
Publication number: 20010023081Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: ApplicationFiled: May 29, 2001Publication date: September 20, 2001Inventors: Roy Yu, Kamalesh S. Desal, Peter A. Franklin, Suryanatayana Kala, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelll, Thomas A. Wassick
-
Patent number: 6281452Abstract: A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.Type: GrantFiled: December 3, 1998Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Chandrika Prasad, Roy Yu, Richard L. Canull, Giulio DiGiacomo, Ajay P. Giri, Lewis S. Goldmann, Kimberley A. Kelly, Bouwe W. Leenstra, Voya R. Markovich, Eric D. Perfecto, Sampath Purushothaman, Joseph M. Sullivan
-
Patent number: 6248599Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: GrantFiled: December 2, 1999Date of Patent: June 19, 2001Assignee: International Business Machines CorporationInventors: Roy Yu, Kamalesh S. Desai, Peter A. Franklin, Suryanarayana Kaja, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelli, Thomas A. Wassick
-
Patent number: 6235412Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.Type: GrantFiled: April 6, 2000Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Ajay P. Giri, Ashwani K. Malhotra, John R. Pennacchia, Eric D. Perfecto, Roy Yu
-
Patent number: 6183588Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: December 14, 1999Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
-
Patent number: 6149048Abstract: An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.Type: GrantFiled: April 8, 1998Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
-
Patent number: 6143117Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: December 14, 1999Date of Patent: November 7, 2000Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
-
Patent number: 6099935Abstract: An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position.Type: GrantFiled: December 15, 1995Date of Patent: August 8, 2000Assignee: International Business Machines CorporationInventors: William Brearley, Laertis Economikos, Paul F. Findeis, Kimberley A. Kelly, Bouwe W. Leenstra, Arthur Gilman Merryman, Eric Daniel Perfecto, Chandrika Prasad, James Patrick Wood, Roy Yu
-
Patent number: 6090633Abstract: A multiple plane pair thin-film structure and a process for the manufacture of that structure. The multiple plane pair thin-film structure is of modular design and manufacture, such that each module comprising the structure is manufactured and tested individually before assembly. The thin film wiring structure is comprised of a plurality of true plane pair thin-film structures. Each such plane pair thin-film structure is manufactured as a module, the functionality of which can be tested for conformity to applicable specifications. Each module is designed and fabricated as a plane pair thin-film structure.Type: GrantFiled: September 22, 1999Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventors: Roy Yu, Chandrika Prasad, John R. Pennacchia, Harvey C. Hamel
-
Patent number: 6083375Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.Type: GrantFiled: November 2, 1998Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Ajay P. Giri, Ashwani K. Malhotra, John R. Pennacchia, Eric D. Perfecto, Roy Yu
-
Patent number: 6054749Abstract: A process for partially repairing defective Multi-Chip Module (MCM) Thin-Film (TF) wiring nets. The process comprises the steps of locating a short circuit between any two nets of the MCM, identifying a site to cut in one of the two nets, and deleting an internal portion of one of the two nets at the identified site.Type: GrantFiled: April 23, 1999Date of Patent: April 25, 2000Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Peter A. Franklin, Carmine J. Mele, Arthur G. Merryman, John R. Pennacchia, Kurt A. Smith, Thomas A. Wassick, Thomas A. Wayson, Roy Yu
-
Patent number: 6048741Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is rotated during the second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.Type: GrantFiled: October 31, 1997Date of Patent: April 11, 2000Assignee: International Business Machines CorporationInventors: Roy Yu, Kamalesh S. Desai, Peter A. Franklin, Suryanarayana Kaja, Kimberley A. Kelly, Yeeling L. Lee, Arthur G. Merryman, Frank R. Morelli, Thomas A. Wassick
-
Patent number: 6036809Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: February 16, 1999Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
-
Patent number: 5972723Abstract: A process for partially repairing defective Multi-Chip Module (MCM) Thin-Film (TF) wiring nets. The process comprises the steps of locating a short circuit between any two nets of the MCM, identifying a site to cut in one of the two nets, and deleting an internal portion of one of the two nets at the identified site.Type: GrantFiled: October 21, 1997Date of Patent: October 26, 1999Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Peter A. Franklin, Carmine J. Mele, Arthur G. Merryman, John R. Pennacchia, Kurt A. Smith, Thomas A. Wassick, Thomas A. Wayson, Roy Yu
-
Patent number: 5937269Abstract: A Process for graphically assisting the partial repair of defective MCM TF wiring nets. The process comprises the steps of inserting the wiring layer of the thin-film device in a tester, scanning the wiring layer of the thin-film device with the tester, identifying defects in the wiring nets, prioritizing the defects based on a function of each of the defective wiring nets, and repairing the defects based on priority.Type: GrantFiled: October 29, 1997Date of Patent: August 10, 1999Assignee: International Business Machines CorporationInventors: Roy Yu, Gerald K. Bartley, Peter A. Franklin, Carmine J. Mele, Arthur G. Merryman, John R. Pennacchia, Kurt A. Smith, Thomas A. Wassick, Thomas A. Wayson