Abstract: A display device includes a pixel array. The pixel array includes multiple pixel elements. At least one pixel element includes an OLED, a first transistor, a second transistor, a third transistor, a first capacitor and a second capacitor. The first transistor has a first terminal coupled to an anode of the OLED for driving the OLED. The second transistor is coupled between a second terminal of the first transistor and a reset voltage and has a control terminal receiving a reset signal. The third transistor is coupled between the anode of the OLED and a control terminal of the first transistor and has a control terminal receiving a compensation signal. The first capacitor is coupled between the control terminal of the first transistor and the anode of the OLED. The second capacitor is coupled to the first capacitor and the control terminal of the first transistor.

Abstract: An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Abstract: A display driving method comprises the steps of: determining a first target-level voltage and a second target-level voltage of a signal of the scan line; determining a first switch time and a second switch time according to an RC loading of the scan line; determining at least one first precharge-level voltage and at least one second precharge-level voltage according to the first target-level voltage, the second target-level voltage, the first switch time, and the second switch time; and outputting the first precharge-level voltage, the first target-level voltage, the second precharge-level voltage, and the second target-level voltage to drive the display panel, wherein the first precharge-level voltage is switched to the first target-level voltage after the first switch time, and the second precharge-level voltage is switched to the second target-level voltage after the second switch time.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: A display device includes pixel units. Each pixel unit includes a driving transistor, a switch transistor, a reset transistor, a light-emitting element, and a control unit. The driving transistor has a control terminal, a first terminal coupled to a first operation voltage source and a second terminal The reset transistor is coupled to the control terminal of the driving transistor. The light-emitting element is coupled to the switch transistor in series between the second terminal of the driving transistor and a second operation voltage source. The control unit stores a threshold voltage of the driving transistor and a driving voltage of the light-emitting element according to a voltage level of the second terminal of the driving transistor. The control unit changes a voltage level of the control terminal of the driving transistor according to the stored threshold voltage, the stored driving voltage, and a corresponding data signal.

Abstract: One embodiment of the invention includes an image compensation module, an OLED display panel, and an OLED display apparatus. A target current value corresponding to a target gray level is stored in a compensation memory portion. A reference gray level and a reference current value corresponding to the reference gray level are stored in a reference memory portion. A compensation gray level can be obtained by an arithmetic compensation unit according to the target current value, reference gray level, reference current value, and gamma parameter. This may reduce the memory space needed for the compensation and reference memory portions, and compensate the images of the display apparatus and panel so that precise colors can be displayed with a high image quality.

Abstract: A display including multiple OLED pixels is provided. Each OLED pixel includes and OLED, a driving transistor, a switch transistor, a first compensation block and a second compensation block. The driving transistor has a first terminal coupled to an anode of the OLED, a second terminal for receiving an operating voltage, and a control terminal for receiving a data voltage. The switch transistor has a first terminal coupled to the control terminal of the driving transistor, a second terminal for receiving the data voltage, and a control terminal for receiving a first control signal. The first compensation block is coupled to the first terminal and the control terminal of the driving transistor. The second compensation block is coupled to the first terminal of the driving transistor, and receives the first control signal and the data voltage.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: An embedded decoupling capacitor wearout monitor for power transmission line, which can be integrated and fabricated in any standard CMOS or BiCMOS circuits. The embedded noise monitor is employed to detect the degraded capacitor and disable it from further operation, which will extend the operation lifetime of the circuit system and prevent subsequent catastrophic failure as a result of hard-breakdown (or capacitor short). In one aspect, the monitor circuit and method detects early degradation signal before catastrophic decoupling capacitor failure and, further can pin-point a degraded decoupling capacitor and disable it, avoiding impact from decoupling capacitor breakdown failure. The monitor circuit and method provides for decoupling capacitor redundancy and includes an embedded and self-diagnostic circuit for functionality and reliability.

Abstract: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.

Abstract: A circuit structure for LCD backlight is disclosed in the present invention. The circuit structure includes an inverter topology, a current balance circuit, and a plurality of loads. The current balance circuit is coupled to the plurality of loads and capable of balancing current of N loads by using N/2?1 balance chokes. The circuit structure may further include a protection circuit which is coupled to the low voltage sides of the plurality of loads. The protection circuit is capable of sensing lamp voltages and providing a feedback signal to a controller. Furthermore, the protection circuit is composed of count-reduced and cost-competitive electronic elements.

Abstract: An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

Abstract: A graded base silicon-germanium (SiGe) heterojunction bipolar transistor (HBT)-based electro-optical (EO) modulator includes a graded base HBT and a light beam directed under the graded base HBT and passing through the free carrier plasma within for the purpose of inducing a phase modulation of the light beam.

Abstract: A pixel structure, a display panel, a display and a driving method thereof are disclosed. The pixel structure comprises an organic light emitting diode, a driving transistor, a storage capacitance, and a switch transistor. A first terminal of the driving transistor receives an image retention cancellation signal. The image retention cancellation signal changes to a second level from a first level before the driving transistor drives the organic light emitting diode so that the driving transistor is operated in a forward curve. A second terminal of the driving transistor is coupled to the light emitting diode. One terminal of the storage capacitance receives a common voltage, and the other terminal of the storage capacitance is coupled to a control terminal of the driving transistor. The switch transistor is controlled by a scan signal to output a data signal to the control terminal of the driving transistor.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: A lighting emitting display, a pixel circuit and a driving method thereof. The pixel circuit includes a driving transistor, a capacitor and a LED. The capacitor receives a first supply voltage and is coupled to a gate of the driving transistor. A cathode of the LED receives a second supply voltage. During a pre-charge period, the gate and the drain of the driving transistor are coupled to an anode of the LED, the source of the driving transistor is coupled to a charging voltage. The source of the driving transistor receives a data signal and the drain and gate of the driving transistor are coupled to each other during a programming period. The source of the driving transistor is coupled to receive the first supply voltage and the drain of the driving transistor is coupled to the anode of the LED during a display period.

Abstract: A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.