Patents by Inventor Ru-Yi Su
Ru-Yi Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145554Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240087962Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
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Patent number: 11908905Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: GrantFiled: July 18, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Publication number: 20240014260Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.Type: ApplicationFiled: June 12, 2023Publication date: January 11, 2024Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Patent number: 11862675Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.Type: GrantFiled: August 31, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
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Patent number: 11854909Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.Type: GrantFiled: July 26, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky
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Publication number: 20230402937Abstract: Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Inventors: Yen-Ku LIN, Ru-Yi SU, Haw-Yun WU, Chun-Lin TSAI
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Patent number: 11676997Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.Type: GrantFiled: June 12, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
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Publication number: 20220359295Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: MAN-HO KWAN, FU-WEI YAO, RU-YI SU, CHUN LIN TSAI, ALEXANDER KALNITSKY
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Publication number: 20220352325Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11450749Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.Type: GrantFiled: May 27, 2020Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11430702Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.Type: GrantFiled: June 6, 2019Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Man-Ho Kwan, Fu-Wei Yao, Ru-Yi Su, Chun Lin Tsai, Alexander Kalnitsky
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Publication number: 20220037518Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.Type: ApplicationFiled: June 9, 2021Publication date: February 3, 2022Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
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Publication number: 20210399087Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
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Publication number: 20210376090Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a buffer layer disposed between an active layer and a substrate. The active layer overlies the substrate. The substrate and the buffer layer include a plurality of pillar structures that extend vertically from a bottom surface of the active layer in a direction away from the active layer. A top electrode overlies an upper surface of the active layer. A bottom electrode underlies the substrate. The bottom electrode includes a conductive body and a plurality of conductive structures that respectively extend continuously from the conductive body, along sidewalls of the pillar structures, to a lower surface of the active layer.Type: ApplicationFiled: May 27, 2020Publication date: December 2, 2021Inventors: Yao-Chung Chang, Chun Lin Tsai, Ru-Yi Su, Wei Wang, Wei-Chen Yang
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Patent number: 11145713Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.Type: GrantFiled: October 15, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
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Patent number: 11069805Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.Type: GrantFiled: December 5, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Hao Yeh, Chih-Chang Cheng, Ru-Yi Su, Ker Hsiao Huo, Po-Chih Chen, Fu-Chih Yang, Chun-Lin Tsai
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Patent number: 10868134Abstract: A channel layer is grown over a substrate, and an active layer is grown over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer. A dielectric layer is deposited over the active layer, and the dielectric layer is patterned to expose a portion of the active layer. A metal diffusion barrier is formed over the exposed portion of the active layer, and a gate is deposited over the metal diffusion barrier.Type: GrantFiled: August 10, 2016Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: King-Yuen Wong, Po-Chih Chen, Chen-Ju Yu, Fu-Chih Yang, Jiun-Lei Jerry Yu, Fu-Wei Yao, Ru-Yi Su, Yu-Syuan Lin
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Publication number: 20200303496Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.Type: ApplicationFiled: June 12, 2020Publication date: September 24, 2020Inventors: Ru-Yi SU, Fu-Chih YANG, Chun Lin TSAI, Chih-Chang CHENG, Ruey-Hsin LIU
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Patent number: 10686032Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.Type: GrantFiled: June 17, 2016Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu