Patents by Inventor Ruben A. Rolda

Ruben A. Rolda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070243643
    Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.
    Type: Application
    Filed: June 22, 2007
    Publication date: October 18, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ruben Rolda, Richard Valerio, Jenny Olero
  • Patent number: 7259043
    Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: August 21, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ruben A. Rolda, Jr., Richard Valerio, Jenny OLero
  • Publication number: 20030215966
    Abstract: A semiconductor wafer design and process having test pads (36) reducing cracks generated during the wafer saw process from extending into and damaging adjacent die. The present invention provides a plurality of circular test pads (36) in a wafer scribe street (34) such that any cracks generated in the test pad during wafer saw self terminate in the periphery of the circular test pad. By providing a curved test pad periphery, cracks will tend to propagate along the edges of the test pads and self terminate therein. The circular test pads avoid any sharp corners as is conventional in rectangular test pads which tend to facilitate the extension of cracks from corners to extend into the adjacent wafer die (32). The present invention utilizes existing semiconductor fab processing and utilizes new reticle sets to define the curved test pads.
    Type: Application
    Filed: May 14, 2002
    Publication date: November 20, 2003
    Inventors: Ruben A. Rolda, Richard Valerio, Jenny Olero
  • Publication number: 20020030261
    Abstract: A semiconductor assembly comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; an interposer of electrically insulating material having a plurality of electrically conductive paths extending through said interposer from the first surface to the second surface, forming electrical terminals on each of said surfaces; said interposer being disposed between said active surfaces of said first and second chips; connections between each of said contact pads of said first chip to selected terminals on said first interposer surface, respectively, and between each of said contact pads of said second chip to selected terminals on said second interposer surface, respectively; and said interposer further having electrical terminals for interconnecting said chips to other parts.
    Type: Application
    Filed: December 18, 2000
    Publication date: March 14, 2002
    Inventors: Ruben A. Rolda, Erwin R. Estepa, Lani Guimbaolibot