Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: In a receiver, a tuner (TUN) converts a reception signal (Srf) to an intermediate-frequency signal (Sif). An adjustable frequency converter (AFRC) converts the intermediate-frequency signal (Sif) to an input signal (Sin) for a filter arrangement (FIL) which is capable of providing various frequency responses (Hfil1, Hfil2) associated with different transmission standards. The adjustable frequency converter (AFRC) and the filter arrangement (FIL) may form part of an integrated receiver-circuit (IRC) suitable for many different transmission standards. The tuner (TUN) may provide the intermediate-frequency signal (Sif) at any one of various different intermediate frequencies (IF1, IF2). For any intermediate frequency (IF1,IF2), the adjustable frequency converter (AFRC) can be adjusted in such a way that the filter arrangement (FIL) receives the input signal (Sin) in a frequency range (FR) which is suitably located with respect to its frequency responses (Hfil1, Hfil2).

Abstract: A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

Abstract: An input circuit for, for example, an A/D converter mainly determines the performance of the circuit preceded by the input circuit (A/D converter). To improve the performance of the input circuit and to overcome the problem of high-power dissipation at the same time, the invention proposes the use of a combined sampling means and sub-ranging means as an input circuit.

Abstract: In a receiver for receiving a modulated carrier (MC) having asymmetrical sidebands (USB,LSB), for example, a TV signal, a synchronous demodulator (SDEM) derives a vectorial baseband signal (VB) from the modulated carrier (MC). A filter (FILT) filters the vectorial baseband signal so as to compensate for the sideband asymmetry, for example, by means of a Nyquist slope. Thus, the sideband asymmetry is compensated at baseband frequencies, rather than at an intermediate frequency, which allows a better quality of reception.

Abstract: In an A/D conversion, digital codes (DC) are obtained on the basis of respective comparisons (A) between an input signal (IN) and at least one reference level (REF). In order to improve the A/D conversion characteristics, the input signal (IN) and the respective reference level (REF) are interchanged (SW) in respect of at least one comparison (A). The digital codes (DC) are processed (POPR) so as to obtain digital output codes (DOC) whose respective signs and magnitudes are, at least on average, substantially independent of any interchanges.

Abstract: To demodulate a quadrature input signal (Si) (for example, frequency shift) a demodulation unit (DEM) is used, comprising a PLL (P) having a complex mixer (M) and a controlled oscillator (V). Normally, a limiter has to be used to keep the loop gain independent of the amplitude of the quadrature input signal. In the PLL, a divider (DEL) is coupled between the mixer (M) and the oscillator (V) to divide the two mixed components (Sm1, Sm2) of the quadrature signal supplied by the mixer.

Abstract: A signal processor has an X-Y rotation circuit and a phase angle control circuit, in the phase angle control circuit, an input phase being approximated by a series of consecutive, in magnitude, decreasing phase angles for forming an output vector by rotation of an input vector over the approximation of the input phase. In the phase angle control circuit, an accuracy of the representation of a phase angle out of the series of phase angles, is dependent on the magnitude of the phase angle, thereby reducing the number of computations in the phase angle control circuit.

Abstract: A signal-processing arrangement includes a conversion circuit CONV which converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) corresponding to different amplitude sub-ranges of the input signal Sin. Each sub-range signal is supplied to a respective one of an array of sampling circuits SC(1)..SC(N) which supplies successive samples thereof to a processing circuit PROC for processing in accordance with operations which may constitute or include A/D conversion. Such an arrangement is particularly suitable for use in a television receiver, multimedia or other video image display apparatus, and various types of disc-players and tape-recorders.

Abstract: In a receiver, both an A/D conversion (ADC) and a phase-split (PSF) is carried out on an input signal (R) to obtain a pair of digital signals (Xd,Yd) which are mutually phase shifted. The pair of digital signals (Xd,Yd) is processed (VSP) as a vectorial signal with a frequency-characteristic which is asymmetrical with respect to zero frequency. In order to make the receiver better suited for relatively low A/D conversion sampling frequencies (Fs), the phase-split (PSF) is carried out prior to the A/D conversion (ADC).

Abstract: A high frequency analog-to-digital converter in which a memory stage receives the result of a series of comparisons of an analog input voltage Vin with a set of reference voltages Vi (where i=0 to Q). Each memory cell Mi (where i=0 to Q) comprises N memory flip-flops L0, L1, . . . LN-1, a multiplexer Mx, and a logic or control module CL. All of the data inputs of the memory flip-flops L0, L1, . . . LN-1 are connected together to the data input of the memory cell. The jth memory flip-flop (where j=0 to N-1) receives at its clock input the clock signal which has been delayed by means of a delay cell having a delay of j.T/N, where T is the period of the clock signal. The data outputs of the N memory flip-flops are connected to the N data inputs of the multiplexer, whose P control inputs receive the P outputs of the control module so that the multiplexer supplies the output signal of the jth memory flip-flop Lj at its output during each (j+1)th fraction of the period T/N.

Abstract: In a folding A/D converter, a comparison part CPM provides a plurality of comparison signals Sc1 . . . Sc9 in response to an input signal Si. The transients in the comparison signals Sc1 . . . Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part LIM effectively selects portions of the transients. A combining part CBM effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part LIM prevents distortion of the folding signal Sf, despite the overlap.

Abstract: An A/D converter has an input part IS which provides differential transitions T1 . . . T.sub.x associated with different levels of an analog input signal. An intermediate part IMS of the converter carries out folding operations and interpolation operations on the transitions to thereby obtain a set of bit-determining signals XO . . . XQ. At least one of the folding and interpolation operations is carried out more than once in alternation with the other of such operations. An output part OS produces a digital output signal from the bit-determining signals. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal processing circuitry. The repetition of at least one of the operations alternately with the other permits the interpolation factor to be increased without necessitating increased complexity of the output part, and the folding factor to be increased without adversely affecting the accuracy of the converter.

Abstract: well as a receiver having low noise and low distortion. These functional units include at least one transadmittance stage having differential transistor pairs coupled in parallel. Gain control is effectuated by varying the unbalance in the differential transistor.

Abstract: Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.

Abstract: Analog-to-digital converter operating in parallel having an analog signal input and a number of digital signal outputs, comprising a plurality of comparators having each two inputs and one output, one input being connected to an impedance network for supplying this one input with its own predetermined reference voltage, and the second input being connected to the analog signal input for receiving an analog input signal to be converted, so that each of the comparators processes a predetermined input signal portion. The comparator outputs are coupled to corresponding digital signal outputs, while delay elements are inserted between the comparator outputs and the corresponding digital signal outputs for causing a delay to occur related to the steepness of the slope of the input signal portion of the relevant comparator.

Abstract: In a clocked comparator with offset reduction, a differential amplifier (5) amplifies the voltage difference between the input terminals (1, 2) and the offset voltage (Voff) in a first state of a clock signal and stores said difference as a charge on the capacitors (C1, C2). In a second state of the clock signal the capacitors are coupled to the inputs (3, 4) of the differential amplifier in such a way that owing to positive feedback the differential amplifier behaves as a flip-flop whose decision threshold is independent of the offset voltage.