Abstract: In a differential amplifier the input signal is applied between a first input terminal (1), formed by the bases of a first (T1) and a third (T3) transistor, and a second input terminal (2), formed by the bases of a second (T2) and a fourth (T4) transistor. The emitters of the third and the fourth transistor are coupled to a first supply-voltage terminal (Vee) by means of a first (J1) and a second (J2) current source, respectively, and to the mutually coupled emitters of the first and the second transistor by means of a first (R1) and a second (R2) resistor. The collectors of the third and the fourth transistor are coupled to a second supply voltage terminal (Vcc) by means of both a fifth resistor (R5) and the base-collector junction of a fifth transistor (T5). The collectors of the first and the second transistors constitute the first (3) and the second (4) output terminal, respectively, and are coupled to the emitter of the fifth transistor by means of a third (R3) and a fourth (R4) resistor.

Abstract: An electronic circuit contains a main stage (10 and 12) that produces a digital code consisting of a plurality of bits (B.sub.1 -B.sub.M-1) that make binary transitions as a function of an input parameter (V.sub.I). A synchronization stage (14 and 16) synchronizes transitions of bits (B.sub.0 -B.sub.K-1) in one part of the code with corresponding transitions of bits (B.sub.K -B.sub.M-1) in another part. When the input parameter is in transition regions where bits in the first-mentioned part of the code could go to wrong values, the synchronization stage suitably replaces the values of bits in the first part with information based on bits in the other part.

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract: An error correction circuit employs a digital averaging technique to overcome transition bit errors in a plurality of original binary bits ideally arranged as a thermometer or circular code. The circuit first generates a like plurality of intermediate signals respectively corresponding to the original bits. Each intermediate signal varies according to a weighted analog summation of a specified odd number of consecutive original bits centered about the corresponding bit. The circuit then compares the intermediate signals with corresponding further signals to produce a corrected code.

Abstract: The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.

Abstract: Various voltage and current sources which are substantially independent of the positive supply rail are provided, some of which are also temperature independent.

Abstract: A double-ended code converter (10) contains three or more like-configured amplifiers (T.sub.O -T.sub.M+1). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply. The second electrodes are selectively coupled to one or the other of a pair of lines (L.sub.B and L.sub.BN) which are coupled to respective load elements (14.sub.B and 14.sub.BN) to provide a pair of complementary signals (V.sub.B and V.sub.BN).

Abstract: A digital-to-analog converter in accordance with the dynamic permutation principle in which a weighted series of accurate reference currents are generated by a cyclic permutation of currents which are equal to each other with a smaller degree of accuracy. The a.c. error component can then be eliminated by averaging the output signal of the converter over one full permutation cycle or an integral multiple thereof so that a signal without the error component is obtained by sampling at the end of every period. The setting of the digital-to-analog converter should not be changed during an averaging period.

Abstract: By means of a controlled integrator, a noise component in the residual signal which is left after a conversion cycle of an analogue-to-digital converter can be eliminated for the major part. It is then possible to digitize this residual signal and thus to obtain additional bit information, as a result of which the range and the resolving power of the analogue-to-digital converter are increased.

Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).

Abstract: A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.

Abstract: An analog-to-digital current converter comprises n series-connected stages which each provide one bit of the Gray code. For this purpose each stage m derives a difference current from the input current (i.sub.i/m), which is the output current (i.sub.0/m-1) of the preceding stage, and a reference current (I/2.sup.m-1) from a source (6). This difference current flows to the output (a) of the stage m (i.sub.o/m) either via a diode (3) or via a current (11) depending on its direction. Conduction of the diode (3) or of the current-mirror circuit (11) is used for the bit indication.This results in a very fast analog-to-digital converter with few components and a high accuracy and resolution.

Abstract: In a digital-to-analog converter (1) a plurality of binary weighted currents are generated, which currents must be in an accurate current ratio relative to each other. By means of a coupling network (15) which is controlled by a control circuit (17), a plurality of currents from said digital-to-analog converter (1) can be coupled to a precision current-mirror circuit (25) in accordance with a cyclic pattern, this allowing deviations in the ratios of the currents from the digital-to-analog converter (1) to be detected by detection means (80) which control correction means (18.2 to 18.16) by means of which the currents from the digital-to-analog converter (1) are corrected so as to reduce the detected deviations.

Abstract: Two current circuits are between two common terminals (+V.sub.B and -V.sub.B). The ratio between the currents in the two current circuits is defined by a first current-dividing circuit, and the absolute values of these currents are defined by means of a second current-dividing circuit, in particular a resistor in this second current-dividing circuit. In order to ensure that the current-stabilizing assumes the proper state upon activation, a first current-supply circuit is coupled to the input of the second current-dividing circuit, which current-supply circuit comprises the series arrangement of a resistor and a transistor arranged as a diode, and a second current-supply circuit is coupled to the output of the current-dividing circuit, which second current-supply circuit includes a transistor whose base is connected in common with that of the transistor of the first current-supply circuit.

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.

Abstract: An amplifier arrangement includes a first section and a second section. The second section has an output transistor which is protected by a protection circuit. The protection circuit acts on the input of the second section in order to obtain a higher gain in the protection loop. In order to preclude instabilities, the protection circuit has a falling frequency response with a flat portion in view of the frequency compensation of the second section.

Abstract: A switching amplifier is described which is intended in particular for sample-and-hold circuits. The switching amplifier has an output stage (T.sub.1, T.sub.2) of the npn-npn-type comprising two output transistors (T.sub.1, T.sub.2) in series. The output (4) is connected to the emitter of a first one (T.sub.1) of the two output transistors (T.sub.1, T.sub.2) and to the collector of the second output transistor (T.sub.2), a diode (T.sub.3) being arranged between the output (4) and this collector. The output (4) can be switched off by switching the voltage on the base of the first transistor (T.sub.1) and the voltage on the point between the diode (T.sub.3) and the collector of the second transistor (T.sub.2) relative to the output voltage, a third transistor (T.sub.4) ensuring that in this situation the collector current of the second transistor (T.sub.2) can be drained when said diode (T.sub.3) is turned off, so that initially said second transistor (T.sub.2) can remain conductive.

Abstract: A current-distribution circuit (1) supplies a plurality of substantially equal currents (i.sub.1, i.sub.2, i.sub.3 and i.sub.4) to a permutation circuit (13), which transfers these currents to outputs (18, 19, 20 and 21) in accordance with a cyclic permutation. The currents in these outputs exhibit a ripple caused by the inequality of the currents (i.sub.1, i.sub.2, i.sub.3 and i.sub.4). A detection circuit (30) detects the ripple component of the currents (i.sub.1, i.sub.2, i.sub.3 and i.sub.4) and applies this ripple component to a associated control circuit of a block of control circuits (50). The relevant control circuit supplies a control current for correcting the relevant current (i.sub.1, i.sub.2, i.sub.3 or i.sub.4) in such way that the ripple component is substantially eliminated.

Abstract: A differential amplifier with single-ended drive includes a balancing impedance (20) coupled between the base of the transistor (3) connected to the signal input (1) and the common point (9) of the two emitters of the transistors (3,4), which form a differential pair. The capacitance value of the capacitor (20) is substantially equal to the capacitance value of the stray capacitance (19) of the collector-substrate junction of a transistor (10) which forms a current source. This provides a symmetry of the capacitances between the input (1) and the common point (9) and between the common point (9) and ground via the transistor (10). This results in an improved balance in the output signals at the output terminals (5,6) and a flat frequency response of the differential amplifier for higher frequencies.

Abstract: For a satisfactory cross-over behavior of the transistors T.sub.1 and T.sub.2 of push-pull amplifier comprising an input 2 and an output 3, it is necessary that the sum of the base-emitter voltages of the transistors T.sub.1 and T.sub.2 remains substantially constant. For this purpose a first voltage-current converter 5 is coupled between the base and the emitter of transistor T.sub.1, the inverting input of this converter being coupled to the base of transistor T.sub.1 via a first reference-voltage source 8 and the non-inverting input to the emitter of transistor T.sub.1. Similarly, a second voltage-current converter 9 and a second reference-voltage source 12 are arranged between the base and the emitter of transistor T.sub.2. The output currents of the first and the second voltage-current converters 5 and 9 are compared with each other in the combining circuit 14 which drives the control amplifier 15, which in its turn controls the base-emitter voltage of transistor T.sub.