Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Abstract: A compliant pin pre-screening, guiding and quality monitoring apparatus is provided. The compliant pin pre-screening, guiding and quality monitoring apparatus includes a fixed plate, a movable plate, a printed circuit board (PCB) and a press-fit connector. The fixed plate defines a through-hole and is disposable above a working table. The movable plate is disposable to be urged by a bias against a first surface of the fixed plate facing the working table and includes pin extendable through the through-hole. The PCB defines a via and is disposable on a second surface of the fixed plate opposite the first surface whereby the pin is extendable through the via with the via corresponding in position to the through-hole and the pin. The press-fit connector is disposable to be secured in position proximate to the PCB and to be inserted into the via with guidance provided by the pin against the bias.

Abstract: An electrostatic protection device (10) includes: a first conductive layer (110), a second conductive layer (140) and a polarization film layer (130), in which the polarization film layer (130) is disposed between the first conductive layer (110) and the second conductive layer (140) and formed of a piezoelectric material which is capable of deforming when applied with electricity; a conductive cantilever (150), disposed on the second conductive layer (140) and including a free end (152); and a charge diffusion layer (170), disposed at a side of the conductive cantilever (150) away from the polarization film layer (130), electrically connected with the first conductive layer (110) and spaced apart from the conductive cantilever (150), in which upon a voltage difference between the first conductive layer (110) and the second conductive layer (140) reaching a predetermined value, the polarization film layer (130) deforms to allow the conductive cantilever (150) to connect with the charge diffusion layer (170).

Abstract: The present application discloses a method for preventing false output of a GOA circuit in a display panel. The method includes providing N clock signals respectively to N GOA units in each of M groups of GOA units cascaded in series. The N clock signals are outputted time-sequentially from a 1st clock signal to a N-th clock signal. The method additionally includes counting a first total number of pulses of the 1st clock signal and a second total number of pulses of the N-th clock signal, comparing each of them to M, and generating a reset signal based on a determination that at least one of the first total number of pulses and the second total number of pulses is smaller than M. The method furthermore includes releasing residual charges of the GOA circuit without outputting any gate-driving signal for a duration of time.

Abstract: A liquid crystal display device and a drive method thereof are disclosed. The liquid crystal display device includes a display panel and a controller. The display panel includes a display region, a plurality of pixels arranged in a matrix are provided in the display region, each of the plurality of pixels includes a red sub-pixel, a blue sub-pixel and a green sub-pixel, and the display region includes a middle portion and a peripheral portion outside the middle portion, and at least one first pixel is provided in the peripheral portion, the controller is configured to relatively increase a luminous intensity of a blue sub-pixel in the first pixel.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: The invention disclose a picosecond-nanosecond laser composite asynchronous ceramics polishing method. First, a picosecond laser is used to scan and irradiate the ceramic surface along the scanning path. At the same time, ceramic surface is initially flattened and the electronic state of materials is removed by picosecond laser to produce micro-nanoparticles. Micro-nanoparticles exist as ionized state in the adjacent space region of irradiated ceramics surface. Then, low energy density nanosecond laser is used according to a preset time to irradiate and melt these micro-nanoparticles which can easily form a dense and smooth fine crystal melting layer to achieve the polishing effect. The present disclosure fixes the generation of micro-cracks and pores in traditional laser polishing process. It overcomes the shortcomings of traditional laser polishing such as large thermal influence zone, easy to generate micro-cracks and pores on the surface, etc.

Abstract: A pressing device includes a screw body. The screw body includes a screw head that comprises a driver interface. The screw body also includes a screw shaft that comprises a screw tip opposite the screw head with respect to the screw shaft, exterior spiral threads between the screw head and screw tip, and an interior cavity with an opening at the screw tip. The pressing device also includes a pin partially inserted into the interior cavity. The pin comprises a first pin end inserted into the interior cavity, a pin shaft that is connected to the first pin end, and a second pin end that is connected to the pin shaft and that is exterior to the interior cavity. Applying a force to the second pin end in a direction towards the screw head causes the pin shaft to advance into to interior cavity.

Abstract: A shift register unit includes: an input circuit, a reset circuit, and an output circuit; a first pull-down control circuit, configured to transmit the first power signal to the first and second pull-down control nodes, and the pull-down node according to the pull-up node, a second pull-down control circuit, configured to transmit a second power signal to the first pull-down control node according to the second power signal, transmit the second power signal to the second pull-down control node according to the first pull-down control node, and transmit the second power signal to the pull-down node according to the second pull-down control node, and a pull-down circuit, configured to transmit the first power signal to the pull-up node and the signal output end according to the pull-down node. The present disclosure may ensure the normal output of the signal and improve the ability of reducing noise.

Abstract: The present invention provides use of a manganese peroxidase in the detoxification of mycotoxins, and specifically, the present invention provides five manganese peroxidases (MnP-1, MnP-2, MnP-4, MnP-5, and MnP-6), genes thereof, and uses thereof. The present invention provides five manganese peroxidases (MnP-1, MnP-2, MnP-4, MnP-5, and MnP-6) derived from lignocellulose degradation bacteria, the amino acid sequences thereof being as set forth in SEQ ID NO: 1, SEQ ID NO: 4, SEQ ID NO: 7, SEQ ID NO: 10, and SEQ ID NO: 13.

Abstract: The present application discloses a shift-register circuit including a shift-register unit and a shutdown-discharge sub-circuit. The shift-register unit is coupled to a clock port, a first reference voltage port, a second reference voltage port, and an output port and configured to set a voltage level at a pull-up node to control a clock signal from the clock port being outputted to the output port to drive a display panel during a display period. The shutdown discharge sub-circuit is configured to at least simultaneously receive a shutdown signal at a first voltage level from a shutdown-discharge control port and a second signal at the first voltage level from the second reference voltage port to start a shutdown period to discharge at least one of the pull-up node and the output port. The shutdown signal has a signal length longer than a signal length of the second signal.

Abstract: A shift register unit includes: an input circuit, a reset circuit, and an output circuit; a first pull-down control circuit, configured to transmit the first power signal to the first and second pull-down control nodes, and the pull-down node according to the pull-up node, a second pull-down control circuit, configured to transmit a second power signal to the first pull-down control node according to the second power signal, transmit the second power signal to the second pull-down control node according to the first pull-down control node, and transmit the second power signal to the pull-down node according to the second pull-down control node, and a pull-down circuit, configured to transmit the first power signal to the pull-up node and the signal output end according to the pull-down node. The present disclosure may ensure the normal output of the signal and improve the ability of reducing noise.

Abstract: There is provided in the present disclosure a shift register unit, including: an input sub-circuit, whose first terminal is coupled to an input signal terminal, and second terminal is coupled to a pull-up node; an output sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to a clock signal terminal, and third terminal is coupled to an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under the control of a level signal of the pull-up node; a first electro-static discharge sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to an electro-static discharge control terminal, and third terminal is coupled to a ground, and configured to discharge static electricity accumulated at the pull-up node under the control of a level signal of the electro-static discharge control terminal.

Abstract: A shift register, a method for driving the same, a gate driving circuit, and a display device are described. The shift register includes a pull-up control circuit which outputs the voltage of a signal input terminal, a pull-up circuit which outputs the voltage of a first clock signal input terminal, a pull-down control circuit which outputs the voltage of a second clock signal input terminal, or pulls down the voltage of the pull-down node, a pull-down circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, a reset circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, and a noise reduction control circuit which outputs the voltage of a noise reduction control signal terminal to the pull-down node in the blanking time of an image frame.

Abstract: The present application discloses a gate driving circuit having multiple shift register units cascaded one after another in multiple stages. The multiple shift register units are grouped into a plurality of groups of shift register units, each of the plurality of groups of shift register units having a plurality of shift register units. Each of the plurality of groups of shift register units includes a single pull-down control sub-circuit.

Abstract: A shift register unit, a shift register circuit and a display panel is provided. The shift register unit includes: an input circuit configured to transmit a power signal to the pull-up node; an output circuit configured to transmit a clock signal to the signal output terminal; a reset circuit configured to transmit a reference signal to the pull-up node and the signal output terminal; a first pull-down control circuit configured to transmit the reference signal to the pull-down control node and the pull-down node; a second pull-down control circuit configured to transmit the power signal to the pull-down control node and the pull-down node; and a pull-down circuit configured to transmit the reference signal to the pull-up node and the signal output terminal.

Abstract: The purpose of the invention is to provide a supported bimetallic core-shell structure catalyst and its preparation method. Supporter, metal salt and reducing agent solution are mixed to synthesize the catalyst M@PdM/ZT by using a one-step synthesis method, wherein the active metal particle M@PdM as core-shell structure, M Is the core representing one of the Ag, Pt, Au and Ir. ZT is the supporter, representing one of hydrotalcite (Mg2Al-LDH), alumina (Al2O3) and silica (SiO2). By changing the temperature and the reaction time to control the kinetic behavior of the reduction of two kinds of metal ions to realize the construction of core-shell structure. Active metal particle composition and shell thickness are regulated by controlling metal ion concentration. The bimetallic core-shell catalyst prepared by this method showed excellent selectivity and stability in acetylene selective hydrogenation and anthraquinone hydrogenation.

Abstract: The present disclosure discloses an electrostatic protection method, an electrostatic protection apparatus and a liquid crystal display. The electrostatic protection method includes: monitoring an interface signal of a timing control circuit and/or a level conversion circuit to determine whether the monitored signal is subjected to electrostatic interference; and when the electrostatic interference is detected, adjusting a timing control signal output by the timing control circuit to a gate driving circuit of an array substrate, wherein the level conversion circuit connects the timing control circuit to the gate driving circuit of the array substrate, and is configured to perform level conversion on an output signal output by the timing control circuit to the gate driving circuit of the array substrate.

Abstract: The purpose of the invention is to provide a supported bimetallic core-shell structure catalyst and its preparation method. Supporter, metal salt and reducing agent solution are mixed to synthesize the catalyst M@PdM/ZT by using a one-step synthesis method, wherein the active metal particle M@PdM as core-shell structure, M Is the core representing one of the Ag, Pt, Au and Ir. ZT is the supporter, representing one of hydrotalcite (Mg2Al-LDH), alumina (Al2O3) and silica (SiO2). By changing the temperature and the reaction time to control the kinetic behavior of the reduction of two kinds of metal ions to realize the construction of core-shell structure. Active metal particle composition and shell thickness are regulated by controlling metal ion concentration. The bimetallic core-shell catalyst prepared by this method showed excellent selectivity and stability in acetylene selective hydrogenation and anthraquinone hydrogenation.

Abstract: A chemical-mechanical polishing pad comprising a thermosetting polyurethane polishing layer includes an isocyanate-terminated urethane prepolymer, a polyamine curative, and a cyclohexanedimethanol curative. The polyamine curative and the cyclohexanedimethanol curative are in a molar ratio of polyamine curative to cyclohexanedimethanol curative in a range from about 20:1 to about 1:1.