Patents by Inventor Rui Ma

Rui Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11645765
    Abstract: Embodiments described herein provide various examples of real-time visual object tracking. In another aspect, a process for performing a local re-identification of a target object which was earlier detected in a video but later lost when tracking the target object is disclosed. This process begins by receiving a current video frame of the video and a predicted location of the target object. The process then places a current search window in the current video frame centered on or in the vicinity of the predicted location of the target object. Next, the process extracts a feature map from an image patch within the current search window. The process further retrieves a set of stored feature maps computed at a set of previously-determined locations of the target object from a set of previously-processed video frames in the video. The process next computes a set of correlation maps between the feature map and each of the set of stored feature maps.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: May 9, 2023
    Assignee: AltumView Systems Inc.
    Inventors: Yu Gao, Xing Wang, Rui Ma, Chao Shen, Minghua Chen, Jie Liang, Jianbing Wu
  • Patent number: 11634694
    Abstract: The present invention provides use of a manganese peroxidase in the detoxification of mycotoxins, and specifically, the present invention provides five manganese peroxidases (MnP-1, MnP-2, MnP-4, MnP-5, and MnP-6), genes thereof, and uses thereof. The present invention provides five manganese peroxidases (MnP-1, MnP-2, MnP-4, MnP-5, and MnP-6) derived from lignocellulose degradation bacteria, the amino acid sequences thereof being as set forth in SEQ ID NO: 1, SEQ ID NO: 4, SEQ ID NO: 7, SEQ ID NO: 10, and SEQ ID NO: 13.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 25, 2023
    Inventors: Bin Yao, Xiaoyun Su, Huang Qin, Huiying Luo, Huoqing Huang, Yingguo Bai, Yuan Wang, Yaru Wang, Rui Ma, Tao Tu, Jianshuang Ma
  • Publication number: 20230108235
    Abstract: This document discusses, among other things, systems and methods to compensate for the effects of temperature on sensors, such as analyte sensor. An example method may include determining a temperature-compensated glucose concentration level by receiving a temperature signal indicative of a temperature parameter of an external component, receiving a glucose signal indicative of an in vivo glucose concentration level, and determining a compensated glucose concentration level based on the glucose signal, the temperature signal, and a delay parameter.
    Type: Application
    Filed: October 6, 2022
    Publication date: April 6, 2023
    Inventors: Anna Harley-Trochimczyk, Sebastian Bohm, Rui Ma, Disha Sheth, Minglian Shi, Kamuran Turksoy
  • Publication number: 20230091934
    Abstract: A performance evaluation device and a design method of a cement for well cementing in a penetrated hydrate layer are provided. The performance evaluation device includes an equivalent wellbore, an inner circulation system, an outer circulation system, a thermal insulation cover, a bracket, a temperature sensing system, and a cement mold. The device can simulate a true downhole situation, conduct an evaluation experiment on the heat insulation performance of a cementing cement, and conduct experiments at different temperatures with automatic temperature control. The design method is to use a low-hydration, early-strength, and heat-insulating cement slurry system during the well cementing in a penetrated hydrate layer, where the low-hydration and early-strength characteristics ensure the effective sealing of a hydrate layer during a cementing process, and the heat insulation characteristic results in low heat conductivity and thus can ensure the stability of a hydrate layer during a production operation.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Applicant: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Yuhuan BU, Shengda SHEN, Chang LU, Huajie LIU, Shenglai GUO, Xun SHAN, Rui MA
  • Publication number: 20230076804
    Abstract: A chemical mechanical polishing pad comprising a polishing portion, the polishing portion comprising: a polymeric body; a plurality of polymer particles embedded within the body of the polymeric body, wherein at least a portion of the plurality of polymer particles is at least partially exposed at a surface of the polymeric body; and a plurality of pores at the surface of the polymeric body.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 9, 2023
    Inventors: Rui MA, Kaiting Li, Jessica Tabert, Sangcheol Kim, Satish Rai
  • Publication number: 20230063437
    Abstract: An intra-layer reinforcement method, and a consolidation and reconstruction simulation experiment system and an evaluation method for a gas hydrate formation are provided. In the intra-layer reinforcement method, the formation reconstruction and fracturing grouting reinforcement technologies are combined; a fracturing grouting process is adopted to create fractures in the gas hydrate formation; and a consolidation liquid enters the fractures and penetrates into the formation through a pressure difference to form a reinforcement with a ribbed slab structure and a specified strength and permeability, which supports the formation to achieve collapse prevention and sand prevention.
    Type: Application
    Filed: April 22, 2022
    Publication date: March 2, 2023
    Applicant: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Yuhuan BU, Huajie LIU, Dong LIN, Shenglai GUO, Chang LU, Xinyang GUO, Rui MA, Qiang WANG, Changyou XIANG, Meihua HUO
  • Publication number: 20230037494
    Abstract: A high-speed real-time data transmission method includes performing deduplication processing on first encoded data from a transmission device to obtain target data. The first encoded data is obtained by encoding corresponding data using a first encoding algorithm. The method further includes encoding the target data using a second encoding algorithm to obtain second encoded data, and sending the second encoded data to a receiving device. A compression ratio of the second encoding algorithm is greater than a compression ratio of the first encoding algorithm.
    Type: Application
    Filed: February 25, 2022
    Publication date: February 9, 2023
    Inventors: Rui MA, Bojie YU, Bin LI
  • Publication number: 20230043196
    Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel, and belongs to the field of display technology. The shift register of the present disclosure includes: an input circuit configured to precharge and reset a pull-up node; one pull-down control circuit being electrically connected to one pull-down circuit through a pull-down node; the pull-down control circuit being configured to control a potential at the pull-down node under a first power voltage; each pull-down circuit being configured to pull down the potential at the pull-down node in response to a potential at the pull-up node; an output circuit configured to output a clock signal through a signal output terminal in response to the potential at the pull-up node; one first noise reduction circuit connected to one pull-down node.
    Type: Application
    Filed: September 15, 2021
    Publication date: February 9, 2023
    Inventors: Yongxian XIE, Tong YANG, Feng QU, Fengzhen LV, Xianjie SHAO, Rui MA, Rui LI
  • Patent number: 11567018
    Abstract: A performance evaluation device and a design method of a cement for well cementing in a penetrated hydrate layer are provided. The performance evaluation device includes an equivalent wellbore, an inner circulation system, an outer circulation system, a thermal insulation cover, a bracket, a temperature sensing system, and a cement mold. The device can simulate a true downhole situation, conduct an evaluation experiment on the heat insulation performance of a cementing cement, and conduct experiments at different temperatures with automatic temperature control. The design method is to use a low-hydration, early-strength, and heat-insulating cement slurry system during the well cementing in a penetrated hydrate layer, where the low-hydration and early-strength characteristics ensure the effective sealing of a hydrate layer during a cementing process, and the heat insulation characteristic results in low heat conductivity and thus can ensure the stability of a hydrate layer during a production operation.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 31, 2023
    Assignee: CHINA UNIVERSITY OF PETROLEUM (EAST CHINA)
    Inventors: Huajie Liu, Yuhuan Bu, Shenglai Guo, Chang Lu, Xinyang Guo, Shengda Shen, Rui Ma
  • Patent number: 11559230
    Abstract: This document discusses, among other things, systems and methods to compensate for the effects of temperature on sensors, such as analyte sensor. An example method may include determining a temperature-compensated glucose concentration level by receiving a temperature signal indicative of a temperature parameter of an external component, receiving a glucose signal indicative of an in vivo glucose concentration level, and determining a compensated glucose concentration level based on the glucose signal, the temperature signal, and a delay parameter.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: January 24, 2023
    Assignee: Dexcom, Inc.
    Inventors: Anna Claire Harley-Trochimczyk, Sebastian Böhm, Rui Ma, Disha B. Sheth, Minglian Shi, Kamuran Turksoy
  • Publication number: 20230012488
    Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.
    Type: Application
    Filed: May 19, 2021
    Publication date: January 19, 2023
    Applicants: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Rui MA, Xiaoye MA, Xianjie SHAO, Ruifang DU
  • Publication number: 20230018612
    Abstract: Provided are a cobalt-free system, a positive electrode slurry, a slurry homogenization method therefor, and the use thereof. The cobalt-free system comprises a cobalt-free material, a binder, a conductive agent and a pH regulator. The cobalt-free system can reduce the rebound degree of the viscosity of a slurry after leaving to stand to the same degree as that of a ternary 811 single crystal, and can also improve the stability of the coating surface density of the cobalt-free material to the same level as that of a ternary material.
    Type: Application
    Filed: October 30, 2020
    Publication date: January 19, 2023
    Applicant: SVolt Energy Technology Co., Ltd.
    Inventors: Xia Su, Hongxin Yang, Xu Gao, Daixing Wang, Bisheng Luo, Rui Ma
  • Publication number: 20220416022
    Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN, Sabih OMAR
  • Publication number: 20220415925
    Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN
  • Publication number: 20220415880
    Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Ayan KAR, Kalyan KOLLURU, Nicholas THOMSON, Rui MA, Benjamin ORR, Nathan JACK, Mauro KOBRINSKY, Patrick MORROW, Chung-Hsun LIN
  • Publication number: 20220415877
    Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Benjamin Orr, Rohit Grover, Nathan Jack, Nicholas Thomson, Rui Ma, Ayan Kar, Kalyan Kolluru
  • Publication number: 20220415276
    Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.
    Type: Application
    Filed: February 19, 2020
    Publication date: December 29, 2022
    Inventors: Rui MA, Xiaoye MA, Ruifang DU
  • Publication number: 20220415881
    Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Rui MA, Kalyan KOLLURU, Nicholas THOMSON, Ayan KAR, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Chung-Hsun LIN
  • Patent number: 11533469
    Abstract: The present application provides a panoramic video picture quality display method and device. Attention position information of a user at different time points in a preset period of time is obtained, the attention position information includes a picture horizontal angle; an attention information curve is created in a polar coordinate system, the attention information curve takes the time point as a polar radius and the picture horizontal angle obtained at the time point as a polar angle; and a picture quality parameter can also be obtained and the picture quality parameter is marked on the attention information curve to display the picture quality parameter.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 20, 2022
    Assignee: KANDAO TECHNOLOGY CO., LTD.
    Inventors: Xiaoke Jiang, Rui Ma, Zhiyou Ma
  • Publication number: 20220396802
    Abstract: Provided are a Cinnamomum burmannii monoterpene synthase CbTPS1, an amino acid sequence thereof, a nucleic acid molecule encoding the protein, an use thereof in preparing the monoterpene synthase, and a method for preparing dextrorotatory borneol by using the Cinnamomum burmannii monoterpene synthase CbTPS1.
    Type: Application
    Filed: November 5, 2020
    Publication date: December 15, 2022
    Applicant: Sichuan Honghe Biotechnology Co., Ltd.
    Inventors: Luqi Huang, Ping Su, Rui Ma, Guanghong Cui, Juan Guo, Baolong Jin, Yating Hu, Jichen Bao