Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Abstract: In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

Abstract: In one embodiment, a tuning network includes: a controllable capacitance; a first switch coupled between the controllable capacitance and a reference voltage node; a second switch coupled between the controllable capacitance and a third switch; the third switch coupled between the second switch and a second voltage node; a fourth switch coupled between the second voltage node and a first inductor; the first inductor having a first terminal coupled to the fourth switch and a second terminal coupled to at least the second switch; and a second inductor having a first terminal coupled to the second terminal of the first inductor and a second terminal coupled to the controllable capacitance.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

Abstract: In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.

Abstract: In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.

Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.