Patents by Inventor Ruilong Xie

Ruilong Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446654
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate contact structures and self-aligned contact process and methods of manufacture. The structure includes: a gate structure having source and drain regions; a first metal contacting the source and drain regions; a second metal over the first metal in the source and drain regions; and a capping material over the first metal and over the gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10446399
    Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 10446653
    Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Lars Wolfgang Liebmann, Hoon Kim
  • Publication number: 20190312028
    Abstract: We report a semiconductor device, containing a semiconductor substrate; an isolation feature on the substrate; a plurality of gates on the isolation feature, wherein each gate comprises a gate electrode and a high-k dielectric layer disposed between the gate electrode and the isolation feature and disposed on and in contact with at least one side of the gate electrode; and a fill metal between the plurality of gates on the isolation feature. We also report methods of forming such a device, and a system for manufacturing such a device.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Chanro Park, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Publication number: 20190312117
    Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.
    Type: Application
    Filed: April 10, 2018
    Publication date: October 10, 2019
    Inventors: Yi Qi, Hsien-Ching Lo, Hong Yu, Yanping Shen, Wei Hong, Xing Zhang, Ruilong Xie, Haiting Wang, Hui Zhan, Yong Jun Shi
  • Patent number: 10439031
    Abstract: Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20190305104
    Abstract: A substrate structure includes a set of nanosheet layers stacked upon a substrate. The substrate structure includes a p-channel region and an n-channel region. The substrate structure further includes divots within the p-channel region and the n-channel region. A first liner is formed within the divots of the n-channel region. The first liner is formed of a material having a positive charge. A second liner is formed within the divots of the p-channel region. The second liner is formed of a material having a negative charge. A p-type epitaxy is deposited in the p-channel region to form first air gap spacers of the divots in the p-channel region. An n-type epitaxy is deposited in the n-channel region to form second air gap spacers of the divots in the n-channel region.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: International Business Machines Corporation
    Inventors: Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita
  • Patent number: 10431663
    Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Balasubramanian Pranatharthiharan, Pietro Montanini, Julien Frougier
  • Patent number: 10431682
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 1, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10431651
    Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie, John H. Zhang
  • Publication number: 20190295898
    Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: September 26, 2019
    Inventors: Ruilong Xie, Daniel Jaeger, Chanro Park, Laertis Economikos, Haiting Wang, Hui Zang
  • Patent number: 10424657
    Abstract: A tri-gate FinFET device includes a fin that is positioned vertically above and spaced apart from an upper surface of a semiconductor substrate, wherein the fin has an upper surface, a lower surface opposite of the upper surface, a first side surface, and a second side surface opposite of the first side surface. The axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the semiconductor substrate, and the first side surface of the fin contacts an insulating material. A gate structure is positioned around the upper surface, the second side surface, and the lower surface of the fin, and a gate contact structure is conductively coupled to the gate structure.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Andreas Knorr
  • Publication number: 20190287863
    Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Edward J. Nowak, Julien Frougier, Jia Zeng
  • Publication number: 20190288117
    Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Ruilong Xie, Julien Frougier, Christopher M. Prindle, Nigel G. Cave
  • Patent number: 10418449
    Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bipul C. Paul, Ruilong Xie, Puneet Harischandra Suvarna
  • Patent number: 10418484
    Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Lars Liebmann, Edward J. Nowak, Julien Frougier, Jia Zeng
  • Patent number: 10410933
    Abstract: This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Min Gyu Sung, Hoon Kim, Hui Zang, Guowei Xu
  • Patent number: 10411010
    Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Murat Kerem Akarvardar, Lars Liebmann, Nigel Graeme Cave
  • Patent number: 10410929
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie
  • Patent number: 10395995
    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 27, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Ruilong Xie, Chun-Chen Yeh