Patents by Inventor Ruilong Xie

Ruilong Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200328121
    Abstract: A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker, Kangguo Cheng, Zhenxing Bi, Ruilong Xie
  • Publication number: 20200328088
    Abstract: A semiconductor device includes a first passivation layer disposed on a semiconductor base. The semiconductor device further includes a dielectric layer disposed on the first passivation layer. The semiconductor device further includes a plurality of pillars disposed in an opening in the dielectric layer and the first passivation layer and from a top surface of the semiconductor base. The semiconductor device further includes a metal layer disposed on the exterior surfaces of the plurality of pillars and sidewalls of the dielectric layer and the first passivation layer and on the exposed top surface of the semiconductor base. The semiconductor device further includes a second passivation layer disposed on the metal layer and a top surface of the semiconductor device; wherein the second passivation layer has an electrical charge.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 10804148
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Patent number: 10804379
    Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an ?-Si layer in a recess over the epi S/D; forming an oxide layer over the ?-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and ?-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Scott Beasor
  • Patent number: 10804199
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yongjun Shi, Ruilong Xie, Nan Fu, Chun Yu Wong
  • Patent number: 10804136
    Abstract: Semiconductor fins of a monolithic semiconductor structure are electrically isolated using a dielectric material at the bottoms of the fins. Relatively tall semiconductor fins can be fabricated at a relatively narrow fin pitch while avoiding mechanical instability. The semiconductor fins are grown on sidewalls of semiconductor mandrels and over a dielectric layer. The semiconductor fins are supported during mandrel removal to provide mechanical stability. The semiconductor fins can be employed as channel regions of FinFET devices.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Chun-Chen Yeh, Tenko Yamashita, Ruilong Xie
  • Patent number: 10804398
    Abstract: A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Julien Frougier, Ruilong Xie
  • Publication number: 20200321244
    Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a dielectric material in a first opening above a first source/drain region in a first region of the semiconductor structure and in a second and a third opening above a respective second and a third source/drain region in a second region of the silicon structure. There is a gate region between the second and third source/drain regions. The method etches away the dielectric material deposited in the first opening and deposits an organic material in the first opening. The method further etches a region above the gate region between the second and third source/drain regions to expose the gate region and form a fourth opening and removes the organic material from the first opening. The method deposits a metal in the first opening and the fourth opening.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 8, 2020
    Inventors: Su Chen Fan, Cheng Chi, Kangguo Cheng, Ruilong Xie
  • Publication number: 20200321448
    Abstract: A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Wenyu XU, Ruilong Xie, Pietro MONTANINI, Hemanth JAGANNATHAN
  • Publication number: 20200321434
    Abstract: A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventors: Kangguo Cheng, Ruilong Xie, Julien Frougier, Chanro Park, TENKO YAMASHITA
  • Patent number: 10796957
    Abstract: Embodiments are directed to a semiconductor device. The semiconductor device includes a first semiconductor fin formed opposite a surface of a first active region of a substrate. The semiconductor device further includes a second semiconductor fin formed opposite a surface of a second active region of the substrate. The semiconductor device further includes a self-aligned buried contact formed over portions of the first active region and the second active region and between the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Jeffrey C. Shearer, Robert C. Wong, Ruilong Xie
  • Patent number: 10797154
    Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 6, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 10797049
    Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
  • Publication number: 20200312718
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Hui ZANG, Ruilong XIE
  • Publication number: 20200312843
    Abstract: An integrated circuit includes a first set of fins, a second set of fins, a gate, and a dielectric plug. The second set of fins is discrete from the first set of fins, and the gate passes over the first set of fins and the second set of fins. The dielectric plug is surrounded by the gate on two sides where the gate passes between the first set of fins and the second set of fins. Incorporation of aspects of the invention into integrated circuits with fin-based field effect transistors (FinFETs) helps to reduce parasitic capacitance between gate features and other nearby electrically conductive features.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Ruilong Xie, Juntao Li, Kangguo Cheng, Chanro Park
  • Publication number: 20200312980
    Abstract: Embodiments of the present invention are directed to forming a reliable wrap-around contact (WAC) without using a source/drain sacrificial region. In a non-limiting embodiment of the invention, an isolation structure is formed over a substrate. A source or drain (S/D) region is formed over the substrate and between sidewalls of the isolation structure. A liner is formed over the S/D region and a sacrificial region is formed over the liner. The sacrificial region can be recessed below a surface of the isolation structure and an interlayer dielectric can be formed over the recessed surface of the sacrificial region. The sacrificial region can be replaced with a wrap-around contact.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Julien Frougier, Kangguo Cheng, RUILONG XIE
  • Publication number: 20200312909
    Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Xin Miao, Richard A. Conti, RUILONG XIE, Kangguo Cheng
  • Publication number: 20200312764
    Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Guoxiang Ning, Ruilong Xie, Lei Sun
  • Patent number: 10790395
    Abstract: A semiconductor device is described. The semiconductor device includes a dielectric layer oriented substantially parallelly to a substrate. The semiconductor device includes a metal layer formed on top of the dielectric layer. The semiconductor device includes a fin extending substantially orthogonally from the substrate through the dielectric layer into the metal layer. The semiconductor device includes a gate insulator deposited on top of the fins and the dielectric layer. The semiconductor device includes an optical projection lithography (OPL) material deposited on a portion of a surface area of the device to form a first covered surface area and a first exposed surface area. The semiconductor device includes a first exposed gate insulator area formed by removing the metal layer under the first exposed surface area. The semiconductor device includes a first exposed fin area formed by removing the gate insulator from the first exposed gate insulator area.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Ruilong Xie, Chanro Park, Min Gyu Sung
  • Patent number: 10788446
    Abstract: A semiconductor device includes a first passivation layer disposed on a semiconductor base. The semiconductor device further includes a dielectric layer disposed on the first passivation layer. The semiconductor device further includes a plurality of pillars disposed in an opening in the dielectric layer and the first passivation layer and from a top surface of the semiconductor base. The semiconductor device further includes a metal layer disposed on the exterior surfaces of the plurality of pillars and sidewalls of the dielectric layer and the first passivation layer and on the exposed top surface of the semiconductor base. The semiconductor device further includes a second passivation layer disposed on the metal layer and a top surface of the semiconductor device; wherein the second passivation layer has an electrical charge.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park