Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first group of field-effect-transistors (FETs); a second group of FETs on top of the first group of FETs; a first half-single-diffusion-break (H-SDB) underneath and being separated from one of the FETs of the second group by a middle-dielectric-insulator (MDI) layer; and a second H-SDB on top of and being separated from one of the FETs of the first group by the MDI layer, where the first H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs, and the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs. A method of forming the same is also provided.

Abstract: A semiconductor structure includes a transistor device at a first side of the semiconductor structure, a control circuit at the first side of the semiconductor structure, and a resistor-capacitor circuit including a resistor and a capacitor. The resistor is in a power delivery network at a second side of the semiconductor structure and the capacitor is at the first side of the semiconductor structure. A first electrode of the capacitor is coupled to a first power rail in the power delivery network at the second side of the semiconductor structure. A second electrode of the capacitor is coupled to a second power rail in the power delivery network at the second side of the semiconductor structure. An input of the control circuit is coupled to the resistor. A gate of the transistor device is coupled to an output of the control circuit.

Abstract: A semiconductor device is provided including NS-FETs in which the active area module, the shallow trench isolation module and the gate module are eliminated from the processing of the semiconductor device. The elimination of these modules makes the overall process easier and aids in reducing the cost of manufacturing the semiconductor device.

Abstract: A semiconductor device includes a first-type transistor, a second-type transistor, and a t-shaped backbone. The first-type transistor includes a first-type source/drain and the second-type transistor includes a second-type source/drain. The t-shaped backbone includes a wall and a sub-wall. The wall separates the first-type transistor and the second-type source/drain. The sub-wall extends from the wall and into the second-type source/drain.

Abstract: Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

Abstract: Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dielectric bar having a left sidewall and a right sidewall; a first nanosheet transistor having a first set of channel nanosheets in direct contact with the left sidewall of the dielectric bar; and a second nanosheet transistor having a second set of channel nanosheets in direct contact with the right sidewall of the dielectric bar, where a first portion of the dielectric bar between the first and the second set of channel nanosheets has a first height; a second portion of the dielectric bar between a first source/drain region of the first nanosheet transistor and a second source/drain region of the second nanosheet transistor has a second height; and the first height is higher than the second height. A method of forming the same is also provided.

Abstract: The embodiments of the present disclosure recognize the potential benefits of semiconductor IC device fabrication techniques to form a microdevice, such as a transistor, that includes structures, such as a source and/or drain, that are to be connected to a backside contact that is further associated with a backside back end of line (BEOL) network. The semiconductor IC device includes a bottom isolation extension (BIE) region. The BIE region is formed within a gate structure of the microdevice and may be located between the backside contact and the gate structure. The BIE region may provide for increased electrical isolation between the backside contact and the gate structure.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first device layer on top of a backside back-end-of-line (BEOL) structure; a middle BEOL structure on top of the first device layer, the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires; a second device layer on top of the middle BEOL structure; a frontside BEOL structure on top of the second device layer; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection form the second device layer to the multiple layers of large pitch wires. A method of forming the same is also provided.

Abstract: A semiconductor structure comprises at least one first nanosheet transistor and at least one second nanosheet transistor disposed on a dielectric layer. The first nanosheet transistor comprises at least one first source/drain region disposed on a side of the first nanosheet transistor. The second nanosheet transistor comprises at least one second source/drain region disposed on a side of the second nanosheet transistor. The second source/drain region has a larger dimension along a given direction than a dimension of the first source/drain region along the given direction. One of a dielectric fill layer and an air gap is disposed in the dielectric layer and under the second source/drain region. A semiconductor layer is disposed under the second source/drain region, in the dielectric layer and around the one of the dielectric fill layer and the air gap.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

Abstract: Embodiments of the invention include a semiconductor structure having nanosheets separated by inner spacers, the inner spacers having a curved portion in a dimension. The semiconductor structure includes source/drain regions formed adjacent to the nanosheets and gate material formed on the nanosheets.

Abstract: A memory device and formation thereof. The memory device includes a stack of memory dies. Each memory die in the stack of memory dies includes two or more layers of memory devices.

Abstract: A semiconductor integrated circuit (IC) device that includes an angled gate cut region, a first transistor associated with a first gate, and a second transistor associated with a second gate. The angled gate cut region may be angled such that its top surface area is nearest a boundary of the first transistor and its bottom surface area is nearest a boundary of the second transistor. The angled gate cut region may separate the first gate from the second gate and may further separate the source/drain regions of the first transistor from the source/drain regions of the second transistor. The angled gate cut region may provide for adequate frontside surface area of the first gate to which a frontside gate contact may connect and may further provide for adequate backside surface area of the second gate to which a backside gate contact may connect.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of lower metal lines in a first metal level; a transition via directly on top of the plurality of lower metal lines; and an upper metal line directly on top of the transition via and the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines, where at least a first lower metal line of the plurality of lower metal lines has a recessed region and a rest region, the recessed region is directly underneath the transition via and filled with a dielectric material; and isolates the rest region of the first lower metal line from the transition via. A method of manufacturing the same is also provided.

Abstract: A method includes forming a first stage of a multi-stage via in a semiconductor structure utilizing processing from a first side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The method also includes forming a second stage of the multi-stage via utilizing processing from a second side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The first surface of the first stage of the multi-stage via is proximate the first side of the semiconductor structure, the first surface of the second stage of the multi-stage via is proximate the second side of the semiconductor structure, and the second surface of the first stage of the multi-stage via abuts the second surface of the second stage of the multi-stage via.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second dielectric bar each having a left sidewall and a right sidewall; a first set of nanosheets having a first end and a second end that is directly adjacent to the left sidewall of the first dielectric bar; a first conductive layer surrounding the first set of nanosheets and directly adjacent to the left sidewall of the first dielectric bar; a second set of nanosheets having a first end and a second end that is directly adjacent to the left sidewall of the second dielectric bar; and a second conductive layer surrounding the second set of nanosheets; directly adjacent to the left sidewall of the second dielectric bar; and separating the second set of nanosheets from the right sidewall of the first dielectric bar. A method of forming the same is also provided.

Abstract: A SRAM is provided that includes a first pull-up transistor having a first channel length, and a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length. The structure further includes a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety thereof, and a second backside contact structure having a vertical portion and a base portion. The vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.

Abstract: The present disclosure describes an illustrative semiconductor IC device that includes a integrated logic microdevice and a memory microdevice that share the same vertical channel. By utilizing the same vertical channel, the overall footprint area of the integrated logic microdevice and the memory microdevice is relatively reduced and allows for further scaling of the associated semiconductor IC device.

Abstract: A semiconductor device comprises a gate cut portion disposed between a first gate region and a second gate region. The gate cut portion comprises a dielectric liner layer disposed around a vacant area. The dielectric liner layer encloses the vacant area, and the gate cut portion isolates the first gate region from the second gate region.