Abstract: A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Abstract: A microelectronic structure including a first transistor including a plurality a first channel layers. A second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. A dielectric bar located between the first transistor and the second transistor. A first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. A first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. A second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.

Abstract: A semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.

Abstract: An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.

Abstract: A semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer and a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below gate spacers of the nanosheet transistor. The backside contact is closer to a backside of the wafer than a frontside of the wafer. The dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.

Abstract: An integrated circuit structure includes a memory cell and multiple transistors therein. The multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. Two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. An active layer is a layer forming a channel in the channel region that is electrically coupled to S/D regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the S/D regions in the corresponding transistor. Methods for forming the integrated circuit structure are disclosed.

Abstract: A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.

Abstract: A semiconductor device includes first source/drain (S/D) epitaxy and a second S/D epitaxy and a gate contact. The device also includes a back end of the line (BEOL) layer connected electrically connected to the first S/D epitaxy and the gate contact on a top side of the device and a wafer that carries the BEOL layer and is on the top side of the device. The device also includes a backside trench epitaxy formed through and contacting portions of the second S/D epitaxy and a backside power distribution network electrically coupled to the backside trench epitaxy and disposed on the bottom of the device.

Abstract: A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Abstract: A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

Abstract: Embodiments herein describe FETs with channels that form wrap-around contacts (a female portion of a female/male connection) with metal contacts (a male portion of the female/male connection) in order to connect the channels to the drain and source regions. In one embodiment, a first conductive contact is formed underneath a dummy channel. In addition an encapsulation material wraps around the first conductive contact. The dummy channel and the encapsulation material can then be removed and replaced by the material of the channel which, as a result, include a female portion that wraps around the first conductive contact.

Abstract: A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Abstract: Techniques for selective CD shrink for source and drain contact trench to optimize FET device performance are provided. In one aspect, a semiconductor FET device includes: at least one gate; source and drains on opposite sides of the at least one gate; recesses in the source and drains; and metal contacts disposed over the source and drains and in the recesses, wherein the metal contacts are in direct contact with a bottom and sidewalls of each of the recesses in both a first direction and a second direction, wherein the first direction is perpendicular to the at least one gate, and wherein the second direction is parallel to the at least one gate. A method of forming a semiconductor FET device is also provided.

Abstract: A skip-level via structure is provided that electrically connects a third level of interconnect wiring to a first level of interconnect wiring or a fourth level of interconnect wiring to a first level of interconnect wiring. In the first instance, the skip-level via structure enables connection even when the first level of interconnect wiring and the third level of interconnect wiring do not line up. In the second instance, the skip-level via structure enables a low resistance connection of the fourth level of interconnect wiring to the first level of interconnect wiring due to increased contact area.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region. A middle section contact is located in the middle gate cut region.

Abstract: A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.

Abstract: A microelectronic structure including a plurality of electronic devices. A plurality of frontside contacts, where each of the plurality of frontside contacts is connected to a frontside of one of the plurality electronic devices, respectively. Each of the plurality of frontside contacts is a same first electric potential. A plurality of backside contacts, where the plurality of backside contacts is connected to a backside of one of the plurality of electronic devices, respectively. Each of the plurality of backside contacts is a same second electrical potential, where the first electrical potential is different than the second electrical potential.

Abstract: A semiconductor device includes a source/drain having a height, a length, and a width. A full wrap-around contact surrounds a partial length of the source/drain, wherein the full wrap-around contact includes a partial front-side wrap-around contact from a front side of a substrate and a partial back-side wrap-around contact from a back side of the substrate.