Abstract: A large capacity ATM core switch architecture is disclosed, which supports multiple traffic classes and quality-of-service (QoS) guarantees. The switch supports both real-time traffic classes with strict QoS requirements, e.g., CBR and VBR, and non-real-time traffic classes with less stringent requirements, e.g., ABR and UBR. The architecture also accommodates real-time and non-real-time multicast flows in an efficient manner. The switch consists of a high-speed core module that interconnects input/output modules with large buffers and intelligent scheduling/buffer management mechanisms. The scheduling can be implemented using a novel dynamic rate control, which controls internal congestion and achieves fair throughput performance among competing flows at switch bottlenecks. In the dynamic rate control scheme, flows are rate-controlled according to congestion information observed at bottleneck points within the switch.

Abstract: A call reception control circuit 1 sets each guaranteed band width required for assuring communication quality of the respective band width demand classes in the corresponding N counter Nc, Ntv and Nv at a certain time interval Ts. The call reception control circuit 1 also sets values defined by the ratio of the W counter Wabr and Wubr of the respective best effort class to use the remained band width. The value 1 is subtracted from each value of the N counter Nc, Ntv and Nv and W counter Wabr and Wubr at every output of the cell from the corresponding class. A priority control process circuit 2 outputs cells to an output channel 3 according to priority levels giving a priority to the band width demand class having the value of the N counter not set to 0 over the band width demand class and the best effort classes having the value of the N counter set to 0.

Abstract: In an ATM switch its method of operation includes accumulating a cell input from an input port in an input multiplex buffer connected to the input port to which the cell has been input; inhibiting output of a cell addressed to a certain output port from an input multiplex buffer when the cell of the certain output port, equal to or more than a threshold value, has been accumulated in the input multiplex buffer; outputting cell, except for the inhibited output cell, from the input multiplex buffer and accumulating the output cell in an output buffer corresponding to an output port of the output cell; outputting cell accumulated in the output buffer and accumulating the output cell in an output separation buffer corresponding to output port of the output cell; and outputting cells accumulated in the output separation buffer to be output to an output port to which the cell is addressed.

Abstract: In the server control section, the number of virtual channel wherein data is being transmitted is counted per service class. The data output rate from each service class corresponds to the number of counted virtual channels in each service class.

Abstract: When a multi-cast cell to be sent to a plurality of output ports is inputted, an address pointer designating the address of storage of the multi-cast cell in the shared buffer is re-cued by copying the cell, for instance from a multi-cast cell address buffer, to address buffers for pertinent output ports. The address pointer of this multi-cast cell is preliminarily stored at a time in small capacity buffers for these output ports and then successively transferred to the address buffers during writing of the multi-cast cell. Since cast cells and multi-cast cells are each given a next address pointer designating an address to be next accessed. A single cast cell and a multi-cast cell are chained via an address cell, which indicates that the succeeding cell is a multi-cast cell. The multi-cast cells in the shared buffer are outputted in a logically re-cued form to their pertinent output ports.

Abstract: A packet switching system comprises input buffers and output buffers, and a self-routing network for routing packets from the input buffers to the output buffers according to the routing information contained in their header. An input controller, associated with each input buffer, includes an idle/busy memory. An output controller associated with each output buffer, detects the idle space of the associated output buffer and determines if the idle space is greater than a predetermined value. If the idle space is determined to be greater than the predetermined value, an idle status bit is generated and if the idle space is determined to be smaller than the predetermined value, a busy status bit is generated. The idle and busy status bits are broadcast to the idle/busy memory of all input controllers.

Abstract: In a multi-stage switching system, a time stamp is attached to each cell at an entry point of the system indicating the time of arrival of the cell, and the cell is transferred to a network comprising multiple switching stages each being composed of basic switching modules. The switching modules of all stages are interconnected to form the network. Each switching module comprises a self-routing switch and buffers connected thereto. The time stamp of cells arriving at a given one of the switching modules, where the cells are likely to arrive out of sequence, is constantly monitored and a minimum value of the time stamps is detected. When an empty buffer exists in the given switching module, an idle cell containing the time stamp of the minimum value is generated at the output of the empty buffer.