Abstract: This application describes systems and methods for generating machine learning models (MLMs). An exemplary method includes obtaining a sample and user input data characterizing a product or service. A subset of the data is selected from the sample based on sampling the sample according to the user input data. An MLM is trained by applying the data subset as training input to the MLM, thereby providing a trained MLM to emulate a customer selection process unique to the product or service. A user interface (UI) configured to receive other user input data and cause the trained MLM to execute on the other user input data, thereby testing the trained MLM, is presented. A summary of results from the execution of the trained MLM is generated and presented in the UI. The summary of results indicates a contribution to the trained MLM of each of a plurality of features.

Abstract: As an indexer indexes and groups events, it can generate data slices that include events. Based on a slice rollover policy, the indexer can add a particular slice to an aggregate slice. Based on an aggregate slice backup policy, the indexer can store a copy of the aggregate slice to a shared storage system. The aggregate slice can be used for restore purposes in the event the indexer fails or becomes unresponsive.

Abstract: An actionable event collector in a server cluster receives information specifying an actionable event instance regarding an actionable event occurrence in the server cluster. The actionable event collector transmits a representation of the actionable event instance to an actionable event queue builder. The actionable event queue builder inserts the representation as an entry into an actionable event queue. The event action dispatcher processes the entry from the actionable event queue, wherein processing the entry comprises determining a responsive action for the entry and causing performance of the responsive action.

Abstract: Cascading payload replication to target compute nodes is disclosed. Cascading payload replication can be accomplished using a two-stage operation for a replication operation. In the first stage, a plan is generated and distributed for the replication operation. The plan includes an assignment of compute nodes to tree nodes in a tree hierarchy. In the second phase, the payload is distributed according to the plan. The plan is different for at least two replication operations. Thus, the cascading payload replication is adaptable to changing target compute nodes and provides for load balancing.

Abstract: A data intake and query system can ingest and index large amounts of data using one or more ingestors and indexers. The ingestors can ingest incoming data and use it to generate events. The ingestor can group the events and prepare them for communication to a message bus. The ingestor can determine a size of the group of events. If the size of the group of events satisfies a message size threshold, the ingestor can store the group of events to a data store, obtain a reference to the group of events, and communicate the reference to the group of events to a message queue. An indexer can obtained the reference from the message queue and use the reference to obtain the group of events from the data store.

Abstract: A data intake and query system can manage the search of large amounts of data using one or more processing nodes. When a new processing node is added or becomes available, the node coordinator can reassign duties from one or more processing nodes to the new processing node. The node coordinator can initially assign the new processing node one or more groups of data for backup purposes. At a later time, the node coordinator can reassign the new processing node to the one or more groups of data for searching purposes.

Abstract: As an indexer indexes and groups events, it can generate data slices that include events. Based on a slice rollover policy, the indexer can add a particular slice to an aggregate slice. Based on an aggregate slice backup policy, the indexer can store a copy of the aggregate slice to a shared storage system. The aggregate slice can be used for restore purposes in the event the indexer fails or becomes unresponsive.

Abstract: Cascading payload replication to target compute nodes is disclosed. Cascading payload replication can be accomplished using a two-stage operation for a replication operation. In the first stage, a plan is generated and distributed for the replication operation. The plan includes an assignment of compute nodes to tree nodes in a tree hierarchy. In the second phase, the payload is distributed according to the plan. The plan is different for at least two replication operations. Thus, the cascading payload replication is adaptable to changing target compute nodes and provides for load balancing.

Abstract: Cascading payload replication to target compute nodes is disclosed. Cascading payload replication can be accomplished using a two-stage operation for a replication operation. In the first stage, a plan is generated and distributed for the replication operation. The plan includes an assignment of compute nodes to tree nodes in a tree hierarchy. In the second phase, the payload is distributed according to the plan. The plan is different for at least two replication operations. Thus, the cascading payload replication is adaptable to changing target compute nodes and provides for load balancing.

Abstract: As an indexer indexes and groups events, it can generate data slices that include events. Based on a slice rollover policy, the indexer can add a particular slice to an aggregate slice. Based on an aggregate slice backup policy, the indexer can store a copy of the aggregate slice to a shared storage system. The aggregate slice can be used for restore purposes in the event the indexer fails or becomes unresponsive.

Abstract: An actionable event responder performs actions including a server cluster determining an actionable event occurrence from a member of a server cluster, determining an event-type code matching the actionable event occurrence, retrieving an event-type response map entry matching the event-type code, and determining, in response to determining that the event-type response map entry matches the event-type code, a response action signifier in the event-type response map entry. The response action signifier indicates a response action performable by the server cluster. The server cluster further detects whether a preauthorization value is set in a dispatch field of the event-type response map entry, and generates an invocation message to a resolution handler based on the preauthorization value being set in the dispatch field of the event-type response map entry. The resolution handler performs the response action to the actionable event occurrence.

Abstract: A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

Abstract: An operational event processor receives information describing operational events arising in relation to a server cluster of a data intake and query system. Responsive actions are identified for the events that are actionable, and those responsive actions are automatically dispatched. Dispatching may include automatically causing the performance of the actions based on remembered preauthorizations, or automatically causing the performance of the actions based on obtaining real time user authorizations. The operational event processor may employ mechanisms to provide extensibility and a high degree of interoperability with other system components.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: A light emitting diode controller integrated circuit includes counter circuitry having inputs coupled to a clock signal input pin, a pulse width modulated signal input pin, and a sense input pin, and has a count output coupled to a gate drive signal output to an external power transistor. The power transistor is connected in series between a power lead, a sense resistor, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor. The counter circuitry provides a Ton_delay equal to a Toff_delay of the power transistor. By counting up during a Ton_delay and down during a Toff_delay, the controller can be used with power transistors of unknown characteristics.

Abstract: A circuit includes a processor that analyzes a pulse width modulated (PWM) signal feedback from a brushless DC motor to determine a transition between a mutual inductance zero crossing condition and a Back Electro Motive Force (BEMF) zero crossing condition of the brushless DC motor. A mutual inductance controller is executed by the processor to commutate the brushless DC motor at startup of the motor when the mutual inductance zero crossing condition is detected by the processor. A BEMF controller is executed by the processor to commutate the brushless DC motor after startup of the motor when the BEMF zero crossing condition is detected by the processor.

Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low.

Abstract: A light emitting diode controller integrated circuit includes counter circuitry having inputs coupled to a clock signal input pin, a pulse width modulated signal input pin, and a sense input pin, and has a count output coupled to a gate drive signal output to an external power transistor. The power transistor is connected in series between a power lead, a sense resistor, and a light emitting diode. The sense input pin is coupled to the series connection between the resistor and the transistor. The counter circuitry provides a Ton_delay equal to a Toff_delay of the power transistor. By counting up during a Ton_delay and down during a Toff_delay, the controller can be used with power transistors of unknown characteristics.