Patents by Inventor Rupesh Singh

Rupesh Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224414
    Abstract: A method for obtaining a metal salt from a spent lithium-ion (Li-ion) battery may include contacting a leaching solvent to a portion of the spent lithium-ion battery to form a first dispersion. The first dispersion is heated to a temperature in a range from 50° C. to 90° C. by applying microwave radiation. The temperature of the first dispersion is maintained to be in the range from 50° C. to 90° C. for a period in a range from 10 seconds to 5 minutes by further applying microwave radiation to the heated first dispersion. The first dispersion is filtered to obtain a first filtrate. A first base is contacted with the first filtrate to increase a pH of the first filtrate to a first predetermined value to precipitate a first metal salt.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: February 11, 2025
    Assignee: AGR LITHIUM INC.
    Inventors: Amol Naik, Rupesh Singh, Vipin Tyagi, Nishchay Chadha
  • Publication number: 20240364347
    Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.
    Type: Application
    Filed: April 1, 2024
    Publication date: October 31, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Rupesh SINGH, Ankur BAL, Kirtiman Singh RATHORE
  • Patent number: 12093193
    Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: September 17, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 12086568
    Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Publication number: 20240295050
    Abstract: A nonwoven fabric having fibers composed of a polymeric blend of a polymer and a high loft additive. The nonwoven fabric exhibits increases in thickness, sound absorbance, and thermal resistance in comparison to a similar nonwoven fabric not having the high loft additive.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 5, 2024
    Applicant: FITESA SIMPSONVILLE, INC.
    Inventors: Mark KALATA, Allan ALVES, Rupesh SINGH
  • Patent number: 11989148
    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: May 21, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Publication number: 20240072320
    Abstract: A method for obtaining a metal salt from a spent lithium-ion (Li-ion) battery may include contacting a leaching solvent to a portion of the spent lithium-ion battery to form a first dispersion. The first dispersion is heated to a temperature in a range from 50° C. to 90° C. by applying microwave radiation. The temperature of the first dispersion is maintained to be in the range from 50° C. to 90° C. for a period in a range from 10 seconds to 5 minutes by further applying microwave radiation to the heated first dispersion. The first dispersion is filtered to obtain a first filtrate. A first base is contacted with the first filtrate to increase a pH of the first filtrate to a first predetermined value to precipitate a first metal salt.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Applicant: AGR LITHIUM INC.
    Inventors: Amol NAIK, Rupesh SINGH, Vipin TYAGI, Nishchay CHADHA
  • Publication number: 20240039545
    Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.
    Type: Application
    Filed: July 7, 2023
    Publication date: February 1, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Rupesh SINGH, Ankur BAL
  • Publication number: 20230369668
    Abstract: A method of obtaining an electrode metal from an electrode of a lithium-ion (Li-ion) battery includes separating an electrode portion from a spent Li-ion battery. A leaching solvent is contacted to the separated electrode portion to form an electrode dispersion. The electrode dispersion is heated to a temperature in a range from about 50° C. to about 90° C. by applying microwave radiation. The temperature of the electrode dispersion is maintained to be in the range from about 50° C. to about 90° C. for a period in a range from about 10 seconds to about 5 minutes by further applying microwave radiation to the heated electrode dispersion. The electrode dispersion is then filtered to obtain the electrode metal.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 16, 2023
    Applicant: AGR LITHIUM INC.
    Inventors: Amol NAIK, Rupesh SINGH, Vipin TYAGI, Nishchay CHADHA
  • Publication number: 20230266387
    Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 24, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Rupesh SINGH, Ankur BAL
  • Publication number: 20230251829
    Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Patent number: 11656848
    Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Publication number: 20230033569
    Abstract: A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.
    Type: Application
    Filed: July 18, 2022
    Publication date: February 2, 2023
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Patent number: 11563443
    Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh
  • Patent number: 11463098
    Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: October 4, 2022
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Ankur Bal, Sri Ram Gupta, Rupesh Singh
  • Patent number: 11417371
    Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 16, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Rupesh Singh, Vivek Tripathi
  • Patent number: 11411565
    Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 9, 2022
    Assignee: STMicroelectronics International N.V.
    Inventors: Rupesh Singh, Ankur Bal
  • Publication number: 20220206987
    Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 30, 2022
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Publication number: 20220188203
    Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 16, 2022
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH
  • Publication number: 20220069837
    Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
    Type: Application
    Filed: July 13, 2021
    Publication date: March 3, 2022
    Applicant: STMicroelectronics International N.V.
    Inventors: Ankur BAL, Rupesh SINGH