Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

Abstract: Pulses having a first width and a second width greater than the first width are generated from a clock signal. An encoded data stream transmitted over a single communications wire is generated by: selecting the pulse having the first width for each bit of the transmit serial data stream having a first logic state; and selecting the pulse having the second width for each bit of the transmit serial data stream having a second logic state. Pulses of the received encoded data stream having the second width are then detected. A first flip-flop logic state is toggled in response to each detected pulse having the second width. A second flip-flop latches the first flip-flop logic state in response to each pulse of the encoded data stream. Outputs of the first and second flip-flops are logically combined to generate a receive serial data stream corresponding to the transmit serial data stream.

Abstract: Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

Abstract: A method for obtaining a metal salt from a spent lithium-ion (Li-ion) battery may include contacting a leaching solvent to a portion of the spent lithium-ion battery to form a first dispersion. The first dispersion is heated to a temperature in a range from 50° C. to 90° C. by applying microwave radiation. The temperature of the first dispersion is maintained to be in the range from 50° C. to 90° C. for a period in a range from 10 seconds to 5 minutes by further applying microwave radiation to the heated first dispersion. The first dispersion is filtered to obtain a first filtrate. A first base is contacted with the first filtrate to increase a pH of the first filtrate to a first predetermined value to precipitate a first metal salt.

Abstract: A method for obtaining a metal salt from a spent lithium-ion (Li-ion) battery may include contacting a leaching solvent to a portion of the spent lithium-ion battery to form a first dispersion. The first dispersion is heated to a temperature in a range from 50° C. to 90° C. by applying microwave radiation. The temperature of the first dispersion is maintained to be in the range from 50° C. to 90° C. for a period in a range from 10 seconds to 5 minutes by further applying microwave radiation to the heated first dispersion. The first dispersion is filtered to obtain a first filtrate. A first base is contacted with the first filtrate to increase a pH of the first filtrate to a first predetermined value to precipitate a first metal salt.

Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

Abstract: A nonwoven fabric having fibers composed of a polymeric blend of a polymer and a high loft additive. The nonwoven fabric exhibits increases in thickness, sound absorbance, and thermal resistance in comparison to a similar nonwoven fabric not having the high loft additive.

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

Abstract: A method for obtaining a metal salt from a spent lithium-ion (Li-ion) battery may include contacting a leaching solvent to a portion of the spent lithium-ion battery to form a first dispersion. The first dispersion is heated to a temperature in a range from 50° C. to 90° C. by applying microwave radiation. The temperature of the first dispersion is maintained to be in the range from 50° C. to 90° C. for a period in a range from 10 seconds to 5 minutes by further applying microwave radiation to the heated first dispersion. The first dispersion is filtered to obtain a first filtrate. A first base is contacted with the first filtrate to increase a pH of the first filtrate to a first predetermined value to precipitate a first metal salt.

Abstract: Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.

Abstract: A method of obtaining an electrode metal from an electrode of a lithium-ion (Li-ion) battery includes separating an electrode portion from a spent Li-ion battery. A leaching solvent is contacted to the separated electrode portion to form an electrode dispersion. The electrode dispersion is heated to a temperature in a range from about 50° C. to about 90° C. by applying microwave radiation. The temperature of the electrode dispersion is maintained to be in the range from about 50° C. to about 90° C. for a period in a range from about 10 seconds to about 5 minutes by further applying microwave radiation to the heated electrode dispersion. The electrode dispersion is then filtered to obtain the electrode metal.

Abstract: An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serial izer without utilizing a deserializer.

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

Abstract: A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.