Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

Abstract: A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.

Abstract: A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.