Abstract: The present invention relates generally to systems and methods for detecting ground faults (i.e., line-to-ground faults) in electrical power conversion systems. In particular, the embodiments described herein include a common mode voltage booster module configured to calculate a common mode voltage boost factor and a common mode voltage boost function based on a plurality of voltage commands for the system. The common mode voltage boost factor and/or the common mode voltage boost function may be applied to the voltage commands to generate boosted voltage commands which, when applied to an inverter or converter, source current indicative of ground faults in the system. More specifically, the common mode voltage boost factor may be multiplied by a common mode voltage calculated by a common mode voltage calculator and summed with the voltage commands.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: The present invention relates generally to systems and methods for detecting ground faults (i.e., line-to-ground faults) in electrical power conversion systems. In particular, the embodiments described herein include a common mode voltage booster module configured to calculate a common mode voltage boost factor and a common mode voltage boost function based on a plurality of voltage commands for the system. The common mode voltage boost factor and/or the common mode voltage boost function may be applied to the voltage commands to generate boosted voltage commands which, when applied to an inverter or converter, source current indicative of ground faults in the system. More specifically, the common mode voltage boost factor may be multiplied by a common mode voltage calculated by a common mode voltage calculator and summed with the voltage commands.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: Control systems, methods and power conversion systems are presented for reducing common mode voltages in AC motor loads driven by inverter PWM control using switching sequences with only active vectors where a first vector of each switching sequence differs by one phase switching state from a last vector of a switching sequence of an adjacent sector, along with enhanced deadtime compensation and reflected wave reduction techniques in providing pulse width modulated switching signals to a switching inverter.

Abstract: A method and apparatus for predicting junction device temperature of at least a first switching device in a power conversion module that includes the first switching device and at least a second switching device, the method comprising the steps of identifying a cross thermal impedance value indicative of how the temperature of the second switching device effects the first switching device temperature and using the cross thermal impedance value to predict the temperature of the at least a first switching device.

Abstract: Multiple inverter motor drives are interconnected in parallel to provide a common output to a motor. Common control circuitry is coupled to all parallel drives via optical cables and provides signals to power layer circuitry of each inverter for generation, at the power layer, of timing for gate drive signals for the respective inverter power electronic switches. The resulting timing exhibits a high degree of synchronicity such that very little imbalance occurs in the outputs of the paralleled drives, resulting in very low circulating currents.

Abstract: A method and apparatus for predicting junction device temperature of at least a first switching device in a power conversion module that includes a plurality of switching devices, the method comprising the steps of, during switching activity, identifying at least one operating characteristic of the first switching device and solving an equation that uses the identified operating characteristic to predict the temperature of the first switching device where the equation solved is a function of the location of the first switching device with respect to the other switching devices in the plurality.

Abstract: The present techniques include methods and systems for operating converter to maintain a lifespan of the converter. In some embodiments, the operating frequency of the converter may be increased such that stress may be reduced on the bond wires of the converter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the converter operating in a maximum power point tracking (MPPT) mode and determining whether the MPPT operation results in aging the converter to a point which reduces the converter lifespan below a desired lifespan. If the MPPT operation reduces the converter lifespan below the desired lifespan, the frequency of the converter may be increased such that the converter may be controlled to operate at a percentage of MPPT. Thus, in some embodiments, power output may be optimized with respect to maintaining a desired lifespan of the converter.

Abstract: The present techniques include methods and systems for operating a wind power system to maintain a lifespan of the rotor side converter. In some embodiments, the current of the rotor side converter may be minimized to reduce the stress and/or junction temperature variation in the switching transistors and bond wires of the converter. More specifically, embodiments involve using a minimal current in the rotor side converter based on the rotor side and grid side reactive powers. If the grid side reactive power is greater than a maximum grid side reactive power, the grid side reactive power may be reduced. Further, if the total reactive power does not meet the grid reactive power requirements, the minimal current in the rotor side converter may be adjusted such that the system may sufficiently power the grid.

Abstract: The present techniques include methods and systems for operating an inverter to maintain a lifespan of the inverter. In some embodiments, the switching frequency and/or the output current of the inverter may be changed such that stress may be reduced on the inverter bond wires of the inverter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the inverter and determining whether the operating conditions result in aging the inverter to a point which reduces the inverter lifespan below a desired lifespan. If the operating conditions reduce the inverter lifespan below the desired lifespan, the switching frequency may be reduced to a lower or minimum switching frequency of the inverter and/or the output current of the inverter may be reduced to a maximum output current at the minimum switching frequency.

Abstract: A system and method for controlling an electrical device is provided. The method comprises receiving three phase power from a source, decomposing signals representative of power in each phase of the three phase power to provide a positive-sequence component of each phase and tracking the positive-sequence component of each phase via a phase locked loop and a tracking filter.

Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. Voltage vectors may be synchronized in a phase-locked-loop configured to maintain synchronous operation of the grid even when the voltages are unbalanced. For example, a phase-locked-loop may be coupled to one or more tracking filters designed to estimate a disturbance in an error signal of the voltages. The estimated disturbance(s) may be removed from the error signal before the phase lock loop determines an estimate of the grid frequency. Thus, adverse affects of voltage unbalance, such as abnormal current behavior, may be mitigated.

Abstract: Methods and systems for tracking an electronic signal corresponding to an operating frequency of an electronic component are provided. A method may include sampling the signal to determine previous and current time samples of the signal. A frequency of interest in the signal may also be pre-warped to decrease adverse warping effects resulting from processing signals having relatively higher operating frequencies. The previous and current time samples of the signals, along with the pre-warped frequency of interest, may be input into a digital tracking filter. The digital tracking filter may be configured to execute one or more algorithms on the previous and current time samples and the pre-warped frequency of interest to estimate a current operating frequency.

Abstract: Provided is a motor controller and method of controlling a motor with an improved maximum junction temperature rating. In accordance with one aspect of the present invention, a motor is controlled by varying a common mode voltage duty ratio for a plurality of solid state switching devices in a power inverter, generating drive signals for the solid state switching devices based at least in part upon the common mode voltage duty ratio, and changing states of the solid state switching devices based upon the drive signals.

Abstract: A method and apparatus for reducing common mode noise in a three phase pulse width modulated (PWM) system, the method comprising the steps of receiving the first, second and third modulating waveforms, identifying one of the modulating waveforms that is at least one of instantaneously the maximum and instantaneously the minimum of the modulating waveforms as a first identified waveform, wherein comparison of the first identified waveform to the carrier signal would generate a first on-off pulse sequence associated with a phase corresponding to the first identified waveform, generating switch control signals associated with the phase corresponding to the first identified waveform that cause a modified on-off pulse sequence that is phase shifted from the first pulse sequence, using the second and third modulating waveforms to generate second and third on-off pulse sequences corresponding to the second and third phases and providing the modified pulse sequence and the second and third pulse sequences to the one

Abstract: Provided is a motor controller and method of controlling a motor with an improved maximum junction temperature rating. In accordance with one aspect of the present invention, a motor is controlled by varying a common mode voltage duty ratio for a plurality of solid state switching devices in a power inverter, generating drive signals for the solid state switching devices based at least in part upon the common mode voltage duty ratio, and changing states of the solid state switching devices based upon the drive signals.

Abstract: A method and apparatus for reducing common mode noise in a three phase pulse width modulated (PWM) system the method comprising the steps of receiving modulating waveforms, identifying a first of the modulating waveforms that is instantaneously the maximum of the modulating waveforms, identifying a second of the modulating waveforms that is instantaneously the minimum of the modulating waveforms, for a first phase associated with at least one of the first and second identified waveforms, substituting a first substitute waveform for the one of the first and second waveforms, for the first phase, modifying at least one of the first substituted waveform and duty cycle signals generated by comparing the first substituted waveform with the carrier signal as a function of a first rule set to substantially minimize the effects of turn on delays and for at least one of the second and third phases, modifying at least one of the associated modulating waveform and duty cycle signals generated by comparing the modulating

Abstract: A method and apparatus for predicting junction device temperature of at least a first switching device in a power conversion module that includes the first switching device and at least a second switching device, the method comprising the steps of identifying a cross thermal impedance value indicative of how the temperature of the second switching device effects the first switching device temperature and using the cross thermal impedance value to predict the temperature of the at least a first switching device.

Abstract: A method and apparatus for predicting junction device temperature of at least a first switching device in a power conversion module that includes a plurality of switching devices, the method comprising the steps of, during switching activity, identifying at least one operating characteristic of the first switching device and solving an equation that uses the identified operating characteristic to predict the temperature of the first switching device where the equation solved is a function of the location of the first switching device with respect to the other switching devices in the plurality.