Patents by Inventor Russell Benson
Russell Benson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038588Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures.Type: ApplicationFiled: July 27, 2022Publication date: February 1, 2024Inventors: Terrence B. McDaniel, Vinay Nair, Russell A. Benson, Christopher W. Petz, Si-Woo Lee, Silvia Borsari, Ping Chieh Chiang, Luca Fumagalli
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Publication number: 20230345708Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Kuo-Chen Wang, Terrence B. McDaniel, Russell A. Benson, Vinay Nair
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Patent number: 11563011Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.Type: GrantFiled: September 30, 2020Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Vinay Nair, Silvia Borsari, Ryan L. Meyer, Russell A. Benson, Yi Fang Lee
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Publication number: 20220246622Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.Type: ApplicationFiled: April 21, 2022Publication date: August 4, 2022Applicant: Micron Technology, Inc.Inventor: Russell A. Benson
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Patent number: 11342336Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.Type: GrantFiled: February 3, 2021Date of Patent: May 24, 2022Assignee: Micron Technology, Inc.Inventor: Russell A. Benson
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Publication number: 20220102348Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Applicant: Micron Technology, Inc.Inventors: Vinay Nair, Silvia Borsari, Ryan L. Meyer, Russell A. Benson, Yi Fang Lee
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Publication number: 20220059469Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.Type: ApplicationFiled: August 21, 2020Publication date: February 24, 2022Inventors: Russell A. Benson, Davide Colombo, Yan Li, Terrence B. McDaniel, Vinay Nair, Silvia Borsari
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Patent number: 11257766Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.Type: GrantFiled: August 21, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventors: Russell A. Benson, Davide Colombo, Yan Li, Terrence B. McDaniel, Vinay Nair, Silvia Borsari
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Patent number: 11189484Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.Type: GrantFiled: December 20, 2019Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Russell A. Benson, Silvia Borsari, Vinay Nair, Ying Rui, Somik Mukherjee
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Patent number: 11164876Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.Type: GrantFiled: February 7, 2019Date of Patent: November 2, 2021Assignee: Micron Technology, Inc.Inventor: Russell A. Benson
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Publication number: 20210193460Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Russell A. Benson, Silvia Borsari, Vinay Nair, Ying Rui, Somik Mukherjee
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Patent number: 11011378Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.Type: GrantFiled: July 1, 2019Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Yiping Wang, Caizhi Xu, Pengyuan Zheng, Ying Rui, Russell A. Benson, Yongjun J. Hu, Jaydeb Goswami
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Publication number: 20210005455Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.Type: ApplicationFiled: July 1, 2019Publication date: January 7, 2021Inventors: Yiping Wang, Caizhi Xu, Pengyuan Zheng, Ying Rui, Russell A. Benson, Yongjun J. Hu, Jaydeb Goswami
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Publication number: 20200258886Abstract: Systems, apparatuses, and methods related to atom implantation for passivation of pillar material are described. An example apparatus includes a pillar of a semiconductor device. The pillar may include a first portion (e.g., a passivation material) formed from silicon nitride and an underlying second portion formed from a conductive material. A region of the first portion opposite from an interface between the first portion and the underlying second portion may be implanted with atoms of an element different from silicon (Si) and nitrogen (N) to enhance passivation of the implanted region.Type: ApplicationFiled: February 7, 2019Publication date: August 13, 2020Inventor: Russell A. Benson
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Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 10134741Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 18, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Methods Of Forming An Elevationally Extending Conductor Laterally Between A Pair Of Conductive Lines
Publication number: 20180019245Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: ApplicationFiled: July 18, 2017Publication date: January 18, 2018Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
Patent number: 9754946Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.Type: GrantFiled: July 14, 2016Date of Patent: September 5, 2017Assignee: Micron Technology, Inc.Inventors: Guangjun Yang, Russell A. Benson, Brent Gilgen, Alex J. Schrinsky, Sanh D. Tang, Si-Woo Lee -
Patent number: 9276001Abstract: A semiconductor device comprises a substrate, a word line, an insulation material, and an etch stop material. The substrate comprises a pillar that may comprise an active area. The word line is formed in the substrate. The insulation material is formed on the word line. The etch stop material is formed on the insulating material and around the pillar.Type: GrantFiled: May 23, 2012Date of Patent: March 1, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Guangjun Yang, Russell Benson
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Publication number: 20140252589Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Micron Technology, Inc.Inventors: James B. Griffin, Russell A. Benson
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Publication number: 20140077126Abstract: Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C4F8 and/or C4F6, an oxygen source, and a carrier gas in combination with tetrafluoroethane (C2F4) or a halofluorocarbon analogue of C2F4.Type: ApplicationFiled: November 20, 2013Publication date: March 20, 2014Applicant: Micron Technology, Inc.Inventors: Russell A. Benson, Theodore M. Taylor, Mark W. Kiehlbauch