Abstract: According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

Abstract: A circuit arrangement, program product and circuit arrangement render stereoscopic images in a multithreaded rendering software pipeline using first and second rendering channels respectively configured to render left and right views for the stereoscopic image. Separate transformations are applied to received vertex data to generate transformed vertex data for use by each of the first and second rendering channels in rendering the left and right views for the stereoscopic image.

Abstract: By mapping leaf nodes of a spatial index to processing elements, efficient distribution of workload in an image processing system may be achieved. In addition, processing elements may use a thread table to redistribute workload from processing elements which are experiencing an increased workload to processing elements which may be idle. Furthermore, the workload experienced by processing elements may be monitored in order to determine if workload is balanced. Periodically the leaf nodes for which processing elements are responsible may be remapped in response to a detected imbalance in workload. By monitoring the workload experienced by the processing elements and remapping leaf nodes to different processing elements in response to unbalanced workload, efficient distribution of workload may be maintained. Efficient distribution of workload may improve the performance of the image processing system.

Abstract: According to embodiments of the invention, a distributed time base signal may be coupled to a memory directory which provides address translation for data located within a memory cache. The memory directory may have attribute bits which indicate whether or not the memory entries have been accessed by the distributed time base signal. Furthermore, the memory directory may have attribute bits which indicate whether or not a memory directory entry should be considered invalid after an access to the memory entry by the distributed time base signal. If the memory directory entry has been accessed by the distributed time base signal and the memory directory entry should be considered invalid after the access by the time base signal, any attempted address translation using the memory directory entry may cause a cache miss. The cache miss may initiate the retrieval of valid data from memory.

Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Abstract: One embodiment of the invention provides a method and apparatus for utilizing memory. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.

Abstract: A computer system includes multiple caches and a cache line state directory structure, having at least a portion dedicated to a particular device cache within a particular device, and contains a fixed number of entries having a one-to-one correspondence to the cache lines of the cache to which it corresponds. The cache line state directory is used to determine whether it is necessary to send an invalidation message to the device cache. In the preferred embodiment, a dedicated portion of the cache line state directory structure corresponds to an I/O bridge device cache. Preferably, the cache line state directory also maintains state for one or more processor caches in a different format. The computer system preferably uses a NUMA architecture, the directories being maintained by node servers in each node.

Abstract: A method and apparatus for communicating between threads in a processor. The method includes reserving a first portion of a cache in a processor for an inbox. The inbox is associated with a first thread being executed by the processor. The method also includes receiving a packet from a second thread, wherein the packet includes an access request. The method further includes using inbox control circuitry for the inbox to process the received packet and determine whether to grant the access request included in the packet.

Abstract: A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

Abstract: A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

Abstract: A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.

Abstract: According to embodiments of the invention, a data structure may be created which may be used by both a ray tracing unit and by a rendering engine. The data structure may have an initial or upper portion representing bounding volumes which partition a three-dimensional scene and a second or lower portion representing objects within the three-dimensional scene. The integrated acceleration data structure may be used by a rendering engine to render a two-dimensional image from a three-dimensional scene, and by a ray tracing unit to perform intersection tests.

Abstract: According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.

Abstract: A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A look-up of a local node directory is performed if a request received at a multi-node bridge of the local node is a system request. If a directory entry indicates that data specified in the request has a local owner or local destination, the request is forwarded to the local node. If the local node determines that the request is a local request, a look-up of the local node directory is performed. If the directory entry indicates that data specified in the request has a local owner and local destination, the coherency of the data on the local node is resolved and a transfer of the request data is performed if required. Otherwise, the request is forwarded to all remote nodes in the multi-node system.

Abstract: A method for maintaining cache coherency for a multi-node system using a specialized bridge which allows for fewer forward progress dependencies. A local node makes a determination whether a request is a local or system request. If the request is a local request, a look-up of a directory in the local node is performed. If an entry in the directory of the local node indicates that data in the request does not have a remote owner and that the request does not have a remote destination, the coherency of the data is resolved on the local node, and a transfer of the data specified in the request is performed if required and if the request is a local request. If the entry indicates that the data has a remote owner or that the request has a remote destination, the request is forwarded to all remote nodes in the multi-node system.

Abstract: According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

Abstract: According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.

Abstract: According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.

Abstract: According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.

Abstract: Embodiments of the invention provide methods and systems to reduce the amount of space necessary to store a spatial index. According to embodiments of the invention, a spatial index may store pointers to information defining primitives which are located within bounding volumes defined by leaf nodes in the spatial index. The pointers may be smaller in size in contrast to information which defines the primitives, and the pointers may point to locations within a scene graph which contains information defining the primitives. Therefore, by storing pointers to primitives in the spatial index rather than the information which defines the primitives, the amount of space required to store the spatial index may be reduced.