Patents by Inventor Russell L. Meyer
Russell L. Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798620Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: GrantFiled: August 1, 2022Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Publication number: 20230329010Abstract: Methods, systems, and devices for trench and pier architectures for three-dimensional memory arrays are described. A semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed to form voids, the pier structures may provide mechanical support of the cross-sectional pattern of the remaining material. In some examples, such pier structures may be formed within or along trenches or other features aligned along a direction of a memory array, which may provide a degree of self-alignment for subsequent operations.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Inventors: Fabio Pellizzer, Russell L. Meyer, Stephen W. Russell, Lorenzo Fratin
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Patent number: 11696454Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: GrantFiled: May 3, 2021Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Publication number: 20230005535Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: ApplicationFiled: July 13, 2022Publication date: January 5, 2023Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Publication number: 20220366974Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Applicant: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Patent number: 11482280Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: GrantFiled: June 10, 2019Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Patent number: 11443799Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: GrantFiled: June 10, 2019Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Patent number: 11404117Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: GrantFiled: February 4, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Publication number: 20210257408Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: ApplicationFiled: May 3, 2021Publication date: August 19, 2021Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Patent number: 10998379Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: GrantFiled: October 18, 2019Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Publication number: 20200243134Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: ApplicationFiled: February 4, 2020Publication date: July 30, 2020Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Patent number: 10622558Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.Type: GrantFiled: March 30, 2018Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Lorenzo Fratin, Russell L. Meyer, Fabio Pellizzer
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Patent number: 10593399Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: GrantFiled: March 19, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Publication number: 20200052035Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Patent number: 10490602Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: GrantFiled: September 21, 2017Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Patent number: 10446226Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: GrantFiled: August 8, 2016Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Publication number: 20190295636Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Russell L. Meyer, Agostino Pirovano, Andrea Redaelli, Lorenzo Fratin, Fabio Pellizzer
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Publication number: 20190287614Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Inventors: Lorenzo Fratin, Fabio Pellizzer, Agostino Pirovano, Russell L. Meyer
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Publication number: 20190088714Abstract: The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Fabio Pellizzer, Russell L. Meyer, Agostino Pirovano, Lorenzo Fratin
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Publication number: 20190044063Abstract: A memory cell can include a chalcogenide material having a narrowed end. A conductive material can be positioned at the narrowed end of the chalcogenide material. A dielectric barrier layer can be disposed between the conductive material and the narrowed end of the chalcogenide material. A dielectric spacer material can be positioned along a narrowed segment of the chalcogenide material.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Lorenzo Fratin, Russell L. Meyer, Fabio Pellizzer