Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

Abstract: The illustrated embodiments relate to a process for improving retention time of a set of integrated circuit devices. The process comprises placing the set of integrated circuit devices in a reverse bias condition, and elevating the surrounding temperature of the set of integrated circuit devices for a predetermined period of time.

Abstract: The illustrated embodiments relate to reducing variable retention time in dynamic random access memory (DRAM) integrated circuit devices. Memory cells that comprise the DRAM device are placed in a reverse bias condition. While under reverse bias, the DRAM device is maintained at an elevated temperature for a predetermined time.

Abstract: The illustrated embodiments relate to reducing variable retention time in dynamic random access memory (DRAM) integrated circuit devices. Memory cells that comprise the DRAM device are placed in a reverse bias condition. While under reverse bias, the DRAM device is maintained at an elevated temperature for a predetermined time.

Abstract: A electrostatic discharge protecting device, to be included in a package carrier assembly, includes shorting elements for shorting the leads together in combination with biasing elements to bias the shorting elements into engagement with the leads and an actuator which is responsive to being inserted into a tester to overcome the biasing element and disengage the shorting elements from the leads and to automatically re-engage the shorting elements to the leads upon removal from the tester.

Abstract: The tester includes a test cabinet which forms an electromagnetic shield enclosure with an aperture in the top wall through which a device under test extends and a thermal hood intersecting the top wall to form a thermal and electromagnetic shield enclosure about the device under test. A device under test receptacle is mounted to a removable electromagnetic shield load board with coaxial connectors which snap into coaxial connectors on a electromagnetic shield mother board which is permanently mounted in the electromagnetic shielded enclosure. The connection of the terminals at the bottom of the mother board are by matched impedance, equal length coaxial cables to the A.C. interface and a ribbon cord to the D.C. interface. The environmental enclosure, the housing are grounded to frame ground and the load board and the mother board are all grounded to instrument ground which is then attached to frame ground via single ground point.

Abstract: The tester includes a test cabinet which forms an electromagnetic shield enclosure with an aperture in the top wall through which a device under test extends and a thermal hood intersecting the top wall to form a thermal and electromagnetic shield enclosure about the device under test. A device under test receptacle is mounted to a removable electromagnetic shield load board with coaxial connectors which snap into coaxial connectors on a electromagnetic shield mother board which is permanently mounted in the electromagnetic shielded enclosure. The connection of the terminals at the bottom of the mother board are by matched impedance, equal length coaxial cables to the A.C. interface and a ribbon cord to the D.C. interface. The environmental enclosure, the housing are grounded to frame ground and the load board and the mother board are all grounded to instrument ground which is then attached to frame ground via single ground point.

Abstract: Method and apparatus for synchronizing data signals with clock pulses in a data transmission computer system having a computer for generating data signals and a local data set for transmitting the data signals to a remotely located data set, includes a receiving register for storing the data signals and a transmitting register coupled to the output of the receiving register for receiving and storing data signals from the receiving register. Logic circuits respond to clock signals from the local data set to cause the data signals to be transferred from the receiving register to the transmitting register and from there to the local data set. The clock pulses from the local data set are synchronized with the data signals as they are stored in the receiving register, the data signals being transferred from the transmitting register to the local data set under the control of the logic circuits in synchronism with the clock signals from the local data set.