Patents by Inventor Ruth A. Brain

Ruth A. Brain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090309227
    Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Inventors: Sean King, Ruth Brain
  • Patent number: 7008872
    Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: March 7, 2006
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Makarem Hussein, Phi L. Nguyen, Ruth A. Brain
  • Patent number: 6958547
    Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: October 25, 2005
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Makarem Hussein, Phi L. Nguyen, Ruth A. Brain
  • Patent number: 6774037
    Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Makarem A. Hussein, Ruth Brain, Robert Turklot, Sam Sivakumar
  • Publication number: 20030216057
    Abstract: A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 20, 2003
    Inventors: Makarem A. Hussein, Ruth Brain, Robert Turklot, Sam Sivakumar
  • Publication number: 20030207560
    Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
    Type: Application
    Filed: May 3, 2002
    Publication date: November 6, 2003
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Makarem A. Hussein, Phi L. Nguyen, Ruth A. Brain
  • Publication number: 20030207561
    Abstract: Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.
    Type: Application
    Filed: May 28, 2003
    Publication date: November 6, 2003
    Inventors: Valery M. Dubin, Chin-Chang Cheng, Makarem A. Hussein, Phi L. Nguyen, Ruth A. Brain
  • Patent number: 6365514
    Abstract: The present invention describes an improved process for forming an aluminum or aluminum alloy plug in the fabrication of a semiconductor device. An opening is formed in a wafer. A titanium wetting layer is then deposited over the wafer and lines the sidewalls and bottom of the opening. A first aluminum deposition step is performed at a first power in a hot deposition chamber. A second aluminum deposition step is performed at a second higher power in a cold deposition chamber. The present invention forms the aluminum plug without the problems of void formation and without reaching temperatures that could cause damage to underlying layers during the fabrication process.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Jick Yu, Ruth Brain
  • Patent number: 6048445
    Abstract: The invention relates to a method of forming a metal line. A photoresist layer is formed on a substrate and patterned so that a metal part on the substrate is exposed. A metal seed layer is then deposited over the photoresist layer utilizing a directional deposition technique. A portion of the metal seed layer is then removed. A metal plating is then formed on the metal seed layer utilizing a technique selected from the group consisting of electroplating and electroless plating. The photoresist layer is then removed.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: April 11, 2000
    Assignee: Intel Corporation
    Inventor: Ruth A. Brain
  • Patent number: 5851319
    Abstract: The present invention discloses a process for selectively annealing heterostructures using microwaves. A heterostructure, comprised of a material having higher microwave absorption and a material having lower microwave absorption, is exposed to microwaves in the cavity. The higher microwave absorbing material absorbs the microwaves and selectively heats while the lower microwave absorbing material absorbs small amounts of microwaves and minimally heats. The higher microwave absorbing material is thereby annealed onto the less absorbing material which is thermally isolated.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: December 22, 1998
    Assignee: California Institute of Technology
    Inventors: Harry A. Atwater, Ruth A. Brain, Martin B. Barmatz
  • Patent number: 5707466
    Abstract: The present invention discloses a process for selectively annealing heterostructures using microwaves. A heterostructure, comprised of a material having higher microwave absorption and a material having lower microwave absorption, is exposed to microwaves in the cavity. The higher microwave absorbing material absorbs the microwaves and selectively heats while the lower microwave absorbing material absorbs small amounts of microwaves and minimally heats. The higher microwave absorbing material is thereby annealed onto the less absorbing material which is thermally isolated.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: January 13, 1998
    Assignee: California Institute of Technology
    Inventors: Harry A. Atwater, Ruth A. Brain, Martin B. Barmatz