Patents by Inventor Ryan J. Goss

Ryan J. Goss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923026
    Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: Seagate Technology LLC
    Inventors: Jeremy B. Goolsby, Ryan J. Goss, Indrajit Prakash Zagade, Thomas V. Spencer, Jeffrey J. Pream, Christopher A. Smith, Charles McJilton
  • Patent number: 11810625
    Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: November 7, 2023
    Assignee: Seagate Technology LLC
    Inventors: Ryan J. Goss, Christopher A. Smith, Indrajit Zagade, Jonathan Henze
  • Patent number: 11698734
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a main memory has memory cells arranged on dies arranged as die sets accessible using parallel channels. A controller is configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among different types of commands executed by the controller responsive to the occurrence rate of the collisions. In further embodiments, the controller may divide a full command into multiple partial commands, each of which are executed as the associated system resources become available. In some cases, the ratio is established between read commands and write commands issued to the main memory.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: July 11, 2023
    Assignee: Seagate Technology LLC
    Inventors: Jonathan M. Henze, Jeffrey J. Pream, Ryan J. Goss
  • Patent number: 11640336
    Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: May 2, 2023
    Assignee: Seagate Technology LLC
    Inventors: Ryan J. Goss, Jack V. Anderson, Jonathan M. Henze
  • Publication number: 20220147279
    Abstract: A solid-state data storage system that does not have a convective cooling capability can arrange a plurality of memory cells into a plurality of logical namespaces with each logical namespace sequentially written, and entirely erased, as a single unit. The logging of data access activity to the plurality of memory cells with a heat module may determine a workload to at least one namespace. The heat module can create an active heat strategy in view of the at least one namespace workload before an active data access operational policy for a first namespace is altered in response to detection of a workload trigger.
    Type: Application
    Filed: November 8, 2021
    Publication date: May 12, 2022
    Inventors: Ryan J. Goss, David W. Claude
  • Publication number: 20220137844
    Abstract: A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 5, 2022
    Inventors: Ryan J. Goss, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell
  • Publication number: 20220115076
    Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 14, 2022
    Inventors: Ryan J. Goss, Christopher A. Smith, Indrajit Zagade, Jonathan Henze
  • Publication number: 20220044754
    Abstract: A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 10, 2022
    Inventors: Jeremy B. Goolsby, Ryan J. Goss, Indrajit Prakash Zagade, Thomas V. Spencer, Jeffrey J. Pream, Christopher A. Smith, Charles McJilton
  • Publication number: 20220035566
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). An apparatus includes a main non-volatile memory (NVM) such as a NAND flash memory. A host command queue lists pending data transfer commands to transfer data between the NVM and a host. For each write command received by the NVM to store write data to an associated target location, a controller examines the host command queue. Based on this review, the controller may direct the NVM to read data adjacent the associated target location to which data are to be written by the write command and to transfer the read data to a read cache. The read data may use some or all of the same resources used to store the write data to the NVM. The read data may be subsequently transferred from the read cache to the host.
    Type: Application
    Filed: July 21, 2021
    Publication date: February 3, 2022
    Inventors: Jonathan M. Henze, Ryan J. Goss
  • Publication number: 20220027234
    Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 27, 2022
    Inventors: Ryan J. Goss, Jack V. Anderson, Jonathan M. Henze
  • Publication number: 20220027069
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a main memory has memory cells arranged on dies arranged as die sets accessible using parallel channels. A controller is configured to arbitrate resources required by access commands to transfer data to or from the main memory using the parallel channels, to monitor an occurrence rate of collisions between commands requiring an overlapping set of the resources, and to adjust a ratio among different types of commands executed by the controller responsive to the occurrence rate of the collisions. In further embodiments, the controller may divide a full command into multiple partial commands, each of which are executed as the associated system resources become available. In some cases, the ratio is established between read commands and write commands issued to the main memory.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 27, 2022
    Inventors: Jonathan M. Henze, Jeffrey J. Pream, Ryan J. Goss
  • Patent number: 10896002
    Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). In some embodiments, a write stream is formed of user data blocks to be sequentially written to a non-volatile memory (NVM). An entry of a reverse directory footer is generated for each user data block in the write stream to describe a physical address in the NVM at which the corresponding user data block is to be stored. The entries are accumulated in a buffer memory until the total count of entries reaches a predetermined threshold and a complete footer data structure is formed. The complete footer data structure is thereafter inserted into the write stream for writing, with the data blocks, to the NVM. The complete footer data structure has an overall size that corresponds to an overall size of each of the user data blocks.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 19, 2021
    Assignee: Seagate Technology LLC
    Inventors: Benjamin J. Scott, Steven S. Williams, Stephen H. Perlmutter, Ryan J. Goss, Daniel J. Benjamin
  • Publication number: 20200004461
    Abstract: Apparatus and method for managing metadata in a data storage device such as a solid-state drive (SSD). In some embodiments, a write stream is formed of user data blocks to be sequentially written to a non-volatile memory (NVM). An entry of a reverse directory footer is generated for each user data block in the write stream to describe a physical address in the NVM at which the corresponding user data block is to be stored. The entries are accumulated in a buffer memory until the total count of entries reaches a predetermined threshold and a complete footer data structure is formed. The complete footer data structure is thereafter inserted into the write stream for writing, with the data blocks, to the NVM. The complete footer data structure has an overall size that corresponds to an overall size of each of the user data blocks.
    Type: Application
    Filed: December 6, 2018
    Publication date: January 2, 2020
    Inventors: Benjamin J. Scott, Steven S. Williams, Stephen H. Perimutter, Ryan J. Goss, Daniel J. Benjamin
  • Patent number: 10452281
    Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: October 22, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jonathan W Haines, Timothy R Feldman, Wayne H Vinson, Ryan J Goss, Kevin Gomez, Mark Allen Gaertner
  • Patent number: 10289305
    Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 14, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Dana L. Simonson, Kristofer C. Conklin, Ryan J. Goss, Robert W. Moss, Stacey Secatch
  • Patent number: 10254969
    Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: April 9, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan J. Goss, Antoine Khoueir, Ara Patapoutian
  • Patent number: 10229052
    Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: March 12, 2019
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna
  • Publication number: 20180349266
    Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna
  • Patent number: 10126964
    Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey Munsil, Jackson Ellis, Ryan J. Goss
  • Publication number: 20180275899
    Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 27, 2018
    Inventors: Jeffrey Munsil, Jackson Ellis, Ryan J. Goss