Patents by Inventor Ryan J. Goss
Ryan J. Goss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180275899Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.Type: ApplicationFiled: May 25, 2017Publication date: September 27, 2018Inventors: Jeffrey Munsil, Jackson Ellis, Ryan J. Goss
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Publication number: 20180253235Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Applicant: SEAGATE TECHNOLOGY LLCInventors: Dana L. Simonson, Kristofer C. Conklin, Ryan J. Goss, Robert W. Moss, Stacey Secatch
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Patent number: 10049040Abstract: The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory is disclosed that includes multiple garbage collection units. The memory also includes a controller that determines whether to select a garbage collection unit of the multiple garbage collection units for garbage collection based on a variable threshold number of the multiple garbage collection units to garbage collect.Type: GrantFiled: January 21, 2011Date of Patent: August 14, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: David S. Ebsen, Ryan J. Goss
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Patent number: 9977597Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.Type: GrantFiled: May 10, 2016Date of Patent: May 22, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Dana L. Simonson, Kristofer C. Conklin, Ryan J. Goss, Robert W. Moss, Stacey Secatch
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Patent number: 9910606Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.Type: GrantFiled: March 23, 2016Date of Patent: March 6, 2018Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Ara Patapoutian, David S. Ebsen, Ryan J. Goss
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Publication number: 20170329525Abstract: Systems and methods for enhanced read recovery based on write time information are described. In one embodiment, the systems and methods include opening a block of flash memory cells for programming, tracking a block open time, and performing a read operation of a programmed page from the block based at least in part on the block open time. In some embodiments, the block includes a plurality of pages, each page including a plurality of flash memory cells. In some cases, the block open time includes an amount of time between the block opening for programming to a time the block closes for programming.Type: ApplicationFiled: May 10, 2016Publication date: November 16, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: Dana L. Simonson, Kristofer C. Conklin, Ryan J. Goss, Robert W. Moss, Stacey Secatch
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Publication number: 20170329532Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, Antoine Khoueir, Ara Patapoutian
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Publication number: 20170277448Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.Type: ApplicationFiled: March 23, 2016Publication date: September 28, 2017Inventors: Antoine Khoueir, Ara Patapoutian, David S. Ebsen, Ryan J. Goss
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Patent number: 9741436Abstract: In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time.Type: GrantFiled: July 9, 2010Date of Patent: August 22, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, Kevin A. Gomez, Mark A. Gaertner
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Publication number: 20160188226Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.Type: ApplicationFiled: November 9, 2015Publication date: June 30, 2016Applicant: SEAGATE TECHNOLOGY LLCInventors: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson, Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Patent number: 9183134Abstract: An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization.Type: GrantFiled: April 22, 2010Date of Patent: November 10, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Jonathan W. Haines, Timothy R. Feldman, Wayne H. Vinson, Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Patent number: 9158700Abstract: A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition.Type: GrantFiled: January 20, 2012Date of Patent: October 13, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, David S. Seekins
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Patent number: 8631294Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: GrantFiled: February 2, 2011Date of Patent: January 14, 2014Assignee: Seagate Technology LLCInventors: Navneeth Kankani, Mark A. Gaertner, Rodney V. Bowman, Ryan J. Goss, David S. Seekins, Tong Shirh Stone
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Publication number: 20130191578Abstract: A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, David S. Seekins
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Patent number: 8458417Abstract: In general, this disclosure relates to garbage collection in a storage device. Aspects of this disclosure describe techniques to identify one or more candidate memory storage blocks that should be recycled during garbage collection. The one or more candidate memory storage blocks may be identified based at least on monitored soft metrics of the candidate memory storage blocks. During garbage collection, the identified one or more candidate memory storage blocks may be recycled to free up storage space.Type: GrantFiled: March 10, 2010Date of Patent: June 4, 2013Assignee: Seagate Technology LLCInventors: Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Patent number: 8438361Abstract: In general, this disclosure relates to storage of logical blocks in a storage device. Aspects of this disclosure describe techniques to monitor the frequency of access of one or more logical blocks referenced by one or more logical block addresses. Based on the frequency of access, in non-limiting aspects of this disclosure, a controller may select one or more physical blocks of a common memory storage block. The storage device may store the logical blocks in the selected physical blocks.Type: GrantFiled: March 10, 2010Date of Patent: May 7, 2013Assignee: Seagate Technology LLCInventors: Ryan J. Goss, Kevin Gomez, Mark Allen Gaertner
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Publication number: 20120191936Abstract: The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory is disclosed that includes multiple garbage collection units. The memory also includes a controller that determines whether to select a garbage collection unit of the multiple garbage collection units for garbage collection based on a variable threshold number of the multiple garbage collection units to garbage collect.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: David S. Ebsen, Ryan J. Goss
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Publication number: 20120124273Abstract: Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: Seagate Technology LLCInventors: Ryan J. Goss, David Scott Seekins, David Scott Ebsen, Navneeth Kankani
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Publication number: 20120110239Abstract: A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, Bernardo Rub
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Publication number: 20120011301Abstract: In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time.Type: ApplicationFiled: July 9, 2010Publication date: January 12, 2012Applicant: Seagate Technology LLCInventors: Ryan J. Goss, Kevin A. Gomez, Mark A. Gaertner