Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).

Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.