Patents by Inventor Ryan T. Hirose
Ryan T. Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10262747Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: GrantFiled: November 8, 2017Date of Patent: April 16, 2019Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 10204691Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: GrantFiled: November 8, 2017Date of Patent: February 12, 2019Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Publication number: 20180068735Abstract: A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.Type: ApplicationFiled: November 8, 2017Publication date: March 8, 2018Applicant: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 9847137Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: August 30, 2016Date of Patent: December 19, 2017Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Publication number: 20170011807Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: August 30, 2016Publication date: January 12, 2017Inventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 9431124Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 20, 2015Date of Patent: August 30, 2016Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Publication number: 20150294731Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 20, 2015Publication date: October 15, 2015Inventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan Georgescu
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Patent number: 9129686Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.Type: GrantFiled: May 23, 2014Date of Patent: September 8, 2015Assignee: Cypress Semiconductor CorporationInventors: Ryan T Hirose, Bogdan I. Georgescu, Leonard Vasile Gitlan, Ashish Ashok Amonkar, Gary Peter Moscaluk, John W. Tiede
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Patent number: 9007843Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.Type: GrantFiled: December 28, 2011Date of Patent: April 14, 2015Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, John W. Tiede, Iustin Ignatescu
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Patent number: 8988938Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: March 17, 2014Date of Patent: March 24, 2015Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Publication number: 20140369136Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.Type: ApplicationFiled: May 23, 2014Publication date: December 18, 2014Applicant: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Bogdan I. Georgescu, Leonard Vasile Gitlan, Ashish Ashok Amonkar, Gary Peter Moscaluk, John W. Tiede
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Publication number: 20140301139Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: ApplicationFiled: March 17, 2014Publication date: October 9, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri, Bogdan I. Georgescu
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Patent number: 8750051Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.Type: GrantFiled: December 29, 2011Date of Patent: June 10, 2014Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Bogdan Georgescu, Leonard Gitlan, Ashish Amonkar, Gary Moscaluk, John Tiede
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Patent number: 8675405Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.Type: GrantFiled: June 18, 2013Date of Patent: March 18, 2014Assignee: Cypress Semiconductor Corp.Inventors: Bogdan Georgescu, Ryan T. Hirose, Igor G. Kouznetsov, Venkatraman Prabhakar, Kaveh Shakeri
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Patent number: 8599618Abstract: A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.Type: GrantFiled: December 29, 2011Date of Patent: December 3, 2013Assignee: Cypress Semiconductor Corp.Inventors: Bogdan I. Georgescu, Ryan T. Hirose
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Patent number: 8570809Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.Type: GrantFiled: December 29, 2011Date of Patent: October 29, 2013Assignee: Cypress Semiconductor Corp.Inventors: Ryan T. Hirose, Bogdan Georgescu, Ashish Amonkar, Sean Mulholland, Vijay Raghavan, Cristinel Zonte
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Patent number: 8542541Abstract: In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.Type: GrantFiled: February 28, 2012Date of Patent: September 24, 2013Assignee: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, Fredrick Jenne, Vijay Srinivasaraghavan, Igor G. Kouznetsov, Paul Fredrick Ruths, Cristinel Zonte, Bogdan Georgescu, Leonard Vasile Gitlan, James Paul Myers
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Publication number: 20130170292Abstract: A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Bogdan I. GEORGESCU, Ryan T. HIROSE
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Publication number: 20130141984Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.Type: ApplicationFiled: December 28, 2011Publication date: June 6, 2013Applicant: Cypress Semiconductor CorporationInventors: Ryan T. Hirose, John Tiede, Iustin Ignatescu
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Publication number: 20130141978Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.Type: ApplicationFiled: December 29, 2011Publication date: June 6, 2013Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Ryan T. HIROSE, Bogdan I. GEORGESCU, Ashish AMONKAR, Sean Brendan MULHOLLAND, Vijay RAGHAVAN, Cristinel ZONTE